02_clock_domain_crossing / task_24 | cdc_bus_sync
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_1/generated.v:2: syntax error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__02_clock_domain_crossing__task_24\samples\run_20260427_200103_669320_45d5dc__sample_1
generated.v previewmodule cdc_bus_sync(
input clk_a, rst_n_a, valid_a, [15:0] data_a,
input clk_b, rst_n_b,
output reg [15:0] data_b, output reg valid_b
);
reg [15:0] data_b_reg;
reg valid_b_reg;
reg valid_b_edge;
always @(posedge clk_a) begin
if (!rst_n_a) begin
data_b_reg <= 0;
valid_b_reg <= 0;
valid_b_edge <= 0;
end else begin
valid_b_edge <= valid_a;
if (valid_b_edge) begin
data_b_reg <= data_a;
valid_b_reg <= 1'b1;
end else begin
valid_b_reg <= 0;
end
end
end
always @(posedge clk_b) begin
if (!rst_n_b) begin
data_b <= 0;
valid_b <= 0;
end else begin
data_b <= data_b_reg;
...
syntax details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_1/generated.v:2: syntax error /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_1/generated.v:1: Errors in port declarations. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_1/functional/generated.v:2: syntax error /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_1/functional/generated.v:1: Errors in port declarations. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_1/generated.v:2: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_1/generated.v:1: Errors in port declarations.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_1/functional/generated.v:2: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_1/functional/generated.v:1: Errors in port declarations.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__02_clock_domain_crossing__task_24\samples\run_20260427_200103_669320_45d5dc__sample_2
generated.v previewmodule cdc_bus_sync(
input clk_a, rst_n_a,
input [15:0] data_a, valid_a,
input clk_b, rst_n_b,
output reg [15:0] data_b, valid_b
);
reg [15:0] data_b_reg;
reg valid_b_reg;
reg valid_b_edge;
always @(posedge clk_a) begin
if (~rst_n_a) begin
data_b_reg <= 0;
valid_b_reg <= 0;
valid_b_edge <= 0;
end else begin
valid_b_edge <= valid_a & ~valid_b_reg;
valid_b_reg <= valid_a;
if (valid_b_edge) begin
data_b_reg <= data_a;
valid_b <= 1'b1;
end else begin
valid_b <= 1'b0;
end
end
end
assign data_b = data_b_reg;
endmodule
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:81: $finish called at 150000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_3 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_3/generated.v:22: error: valid_b Unable to assign to unresolved wires. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__02_clock_domain_crossing__task_24\samples\run_20260427_200103_669320_45d5dc__sample_3
generated.v previewmodule cdc_bus_sync(
input clk_a, rst_n_a,
input [15:0] data_a, valid_a,
input clk_b, rst_n_b,
output reg [15:0] data_b, valid_b
);
reg data_b_sync;
reg valid_b_sync;
reg valid_b_edge;
always @(posedge clk_a) begin
if (!rst_n_a) begin
data_b_sync <= 0;
valid_b_sync <= 0;
valid_b_edge <= 0;
end else begin
valid_b_edge <= valid_a & ~valid_b_sync;
valid_b_sync <= #1 valid_a;
if (valid_b_edge) begin
data_b_sync <= data_a;
valid_b <= #1 1'b1;
end else begin
valid_b <= 0;
end
end
end
assign data_b = data_b_sync;
assign valid_b = valid_b_sync;
endmodule
syntax details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_3/generated.v:22: error: valid_b Unable to assign to unresolved wires. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_3/generated.v:24: error: valid_b Unable to assign to unresolved wires. 2 error(s) during elaboration. functional details[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_3/functional/generated.v:22: error: valid_b Unable to assign to unresolved wires.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_3/functional/generated.v:24: error: valid_b Unable to assign to unresolved wires.
/workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:15: warning: Port 4 (valid_a) of cdc_bus_sync expects 16 bits, got 1.
/workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:15: : Padding 15 high bits of the port.
/workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:15: warning: Port 8 (valid_b) of cdc_bus_sync expects 16 bits, got 1.
/workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:15: : Padding 15 high bits of the port.
warning: Found both default and explicit timescale based delays. Use
: -Wtimescale to find the design element(s) with no explicit
: timescale.
2 error(s) during elaboration.
synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_3/generated.v:22: error: valid_b Unable to assign to unresolved wires.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_3/generated.v:24: error: valid_b Unable to assign to unresolved wires.\n2 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_3/functional/generated.v:22: error: valid_b Unable to assign to unresolved wires.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_3/functional/generated.v:24: error: valid_b Unable to assign to unresolved wires.\n/workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:15: warning: Port 4 (valid_a) of cdc_bus_sync expects 16 bits, got 1.\n/workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:15: : Padding 15 high bits of the port.\n/workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:15: warning: Port 8 (valid_b) of cdc_bus_sync expects 16 bits, got 1.\n/workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:15: : Padding 15 high bits of the port.\nwarning: Found both default and explicit timescale based delays. Use\n : -Wtimescale to find the design element(s) with no explicit\n : timescale.\n2 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_200103_669320_45d5dc | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: Data corrupted during transfer. Expected FFFF, got 0000 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__02_clock_domain_crossing__task_24\samples\run_20260427_200103_669320_45d5dc__sample_4
generated.v previewmodule cdc_bus_sync(
input clk_a, rst_n_a,
input [15:0] data_a, valid_a,
input clk_b, rst_n_b,
output reg [15:0] data_b, valid_b
);
reg data_b_reg;
reg valid_b_reg;
reg valid_a_sync;
reg valid_a_edge;
always @(posedge clk_a) begin
if (!rst_n_a) begin
valid_a_sync <= 0;
end else begin
valid_a_sync <= valid_a;
end
end
always @(posedge clk_b) begin
if (!rst_n_b) begin
valid_b_reg <= 0;
data_b_reg <= 0;
end else begin
valid_b_reg <= valid_a_sync;
if (valid_a_edge) begin
data_b_reg <= data_a;
end
end
end
...
functional details[stdout] ERROR: Data corrupted during transfer. Expected FFFF, got 0000 TEST_FAILED /workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:81: $finish called at 135000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: Data corrupted during transfer. Expected FFFF, got 0000",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__02_clock_domain_crossing__task_24\samples\run_20260427_200103_669320_45d5dc__sample_5
generated.v previewmodule cdc_bus_sync(
input clk_a, rst_n_a,
input [15:0] data_a, valid_a,
input clk_b, rst_n_b,
output reg [15:0] data_b, valid_b
);
reg valid_b_sync;
reg valid_b_edge;
always @(posedge clk_a) begin
if (!rst_n_a) begin
valid_b_sync <= 0;
valid_b_edge <= 0;
end else begin
valid_b_sync <= valid_a;
valid_b_edge <= ~valid_b_edge & valid_b_sync;
end
end
always @(posedge clk_b) begin
if (!rst_n_b) begin
data_b <= 0;
valid_b <= 0;
end else begin
if (valid_b_edge) begin
data_b <= data_a;
valid_b <= 1;
end else begin
valid_b <= 0;
end
end
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:81: $finish called at 158000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_6 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_6/generated.v:2: syntax error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__02_clock_domain_crossing__task_24\samples\run_20260427_200103_669320_45d5dc__sample_6
generated.v previewmodule cdc_bus_sync(
input clk_a, rst_n_a, valid_a, [15:0] data_a,
input clk_b, rst_n_b,
output reg [15:0] data_b, output reg valid_b
);
reg data_b_reg;
reg valid_b_reg;
reg valid_a_sync;
always @(posedge clk_a) begin
if (!rst_n_a) begin
valid_a_sync <= 0;
end else begin
valid_a_sync <= valid_a;
end
end
always @(posedge clk_b) begin
if (!rst_n_b) begin
data_b <= 0;
valid_b <= 0;
end else begin
if (valid_a_sync) begin
data_b <= data_a;
valid_b <= 1;
end else begin
valid_b <= 0;
end
end
end
...
syntax details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_6/generated.v:2: syntax error /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_6/generated.v:1: Errors in port declarations. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_6/functional/generated.v:2: syntax error /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_6/functional/generated.v:1: Errors in port declarations. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_6/generated.v:2: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_6/generated.v:1: Errors in port declarations.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_6/functional/generated.v:2: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__02_clock_domain_crossing__task_24/sample_6/functional/generated.v:1: Errors in port declarations.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__02_clock_domain_crossing__task_24\samples\run_20260427_200103_669320_45d5dc__sample_7
generated.v previewmodule cdc_bus_sync(
input clk_a, rst_n_a, valid_a,
input clk_b, rst_n_b,
input [15:0] data_a,
output reg [15:0] data_b,
output reg valid_b
);
reg valid_a_sync;
reg valid_b_edge;
always @(posedge clk_a) begin
if (!rst_n_a) begin
valid_a_sync <= 0;
end else begin
valid_a_sync <= valid_a;
end
end
always @(posedge clk_b) begin
if (!rst_n_b) begin
valid_b_edge <= 0;
data_b <= 0;
valid_b <= 0;
end else begin
if (valid_a_sync) begin
valid_b_edge <= 1;
end
if (valid_b_edge) begin
data_b <= data_a;
valid_b <= 1;
end else begin
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:81: $finish called at 146000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_8 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__02_clock_domain_crossing__task_24\samples\run_20260427_200103_669320_45d5dc__sample_8
generated.v previewmodule cdc_bus_sync(
input clk_a, rst_n_a, valid_a,
input clk_b, rst_n_b,
input [15:0] data_a,
output reg [15:0] data_b,
output reg valid_b
);
reg valid_b_sync;
reg valid_b_edge;
always @(posedge clk_a) begin
if (!rst_n_a) begin
valid_b_sync <= 0;
valid_b_edge <= 0;
end else begin
valid_b_sync <= valid_a;
valid_b_edge <= valid_b_sync & ~valid_b;
end
end
always @(posedge clk_b) begin
if (!rst_n_b) begin
data_b <= 0;
valid_b <= 0;
end else begin
if (valid_b_edge) begin
data_b <= data_a;
valid_b <= 1;
end else begin
valid_b <= 0;
end
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:81: $finish called at 158000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_9 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__02_clock_domain_crossing__task_24\samples\run_20260427_200103_669320_45d5dc__sample_9
generated.v previewmodule cdc_bus_sync(
input clk_a, rst_n_a,
input [15:0] data_a, valid_a,
input clk_b, rst_n_b,
output reg [15:0] data_b, valid_b
);
reg valid_b_sync;
reg valid_b_edge;
always @(posedge clk_a) begin
if (~rst_n_a) begin
valid_b_sync <= 0;
valid_b_edge <= 0;
end else begin
valid_b_sync <= valid_a;
if (valid_a && !valid_b_edge) begin
valid_b_edge <= 1;
end else begin
valid_b_edge <= 0;
end
end
end
always @(posedge clk_b) begin
if (~rst_n_b) begin
data_b <= 0;
valid_b <= 0;
end else begin
if (valid_b_edge) begin
data_b <= data_a;
valid_b <= 1;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:81: $finish called at 135000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_10 | run_20260427_200103_669320_45d5dc | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: Simulation timed out. valid_b was never asserted. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__02_clock_domain_crossing__task_24\samples\run_20260427_200103_669320_45d5dc__sample_10
generated.v previewmodule cdc_bus_sync(
input clk_a, rst_n_a,
input [15:0] data_a, valid_a,
input clk_b, rst_n_b,
output reg [15:0] data_b, valid_b
);
reg valid_b_sync;
reg valid_b_edge;
always @(posedge clk_a) begin
if (!rst_n_a) begin
valid_b_sync <= 0;
valid_b_edge <= 0;
end else begin
valid_b_sync <= valid_a;
valid_b_edge <= valid_b_sync & ~valid_b_sync_d;
end
end
always @(posedge clk_b) begin
if (!rst_n_b) begin
data_b <= 0;
valid_b <= 0;
end else begin
if (valid_b_edge) begin
data_b <= data_a;
valid_b <= 1;
end else begin
valid_b <= 0;
end
end
...
functional details[stdout] ERROR: Simulation timed out. valid_b was never asserted. TEST_FAILED /workspace/banchmarks/pashencev/02_clock_domain_crossing/task_24/tb.v:89: $finish called at 1000000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: Simulation timed out. valid_b was never asserted.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|