03_low_power_design / task_34 | soc_top
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | valid in assign l-value: &(pwr_enable) |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260427_200103_669320_45d5dc__sample_1
generated.v previewmodule soc_top(
input clk,
input rst_n,
input sleep_req,
input [31:0] data_in,
output reg [31:0] data_out,
output reg pwr_enable,
output reg iso_en
);
// Instantiate submodules
aon_ctrl aon_ctrl(.clk(clk), .rst_n(rst_n), .sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
pd_dsp pd_dsp(.clk(clk), .data_in(data_in), .data_out(&data_out));
endmodule
module aon_ctrl(
input clk,
input rst_n,
input sleep_req,
output reg pwr_enable,
output reg iso_en
);
always @(posedge clk) begin
if (rst_n) begin
pwr_enable <= 1'b1;
iso_en <= 1'b0;
end else begin
if (sleep_req) begin
iso_en <= 1'b1;
pwr_enable <= 1'b1;
...
syntax details[stderr] valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `soc_top.pd_dsp' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:49: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `tb_task_34.dut.pd_dsp' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:49: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `soc_top.pd_dsp'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:49: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `tb_task_34.dut.pd_dsp'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:49: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | ion not valid in assign l-value: &(pwr_enable) |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260427_200103_669320_45d5dc__sample_2
generated.v previewmodule soc_top(
input clk,
input rst_n,
input sleep_req,
input [31:0] data_in,
output reg [31:0] data_out,
output reg pwr_enable,
output reg iso_en
);
// Instantiate submodules
aon_ctrl aon_ctrl(.clk(clk), .rst_n(rst_n), .sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
pd_dsp pd_dsp(.clk(clk), .data_in(data_in), .data_out(&data_out));
endmodule
module aon_ctrl(
input clk,
input rst_n,
input sleep_req,
output reg pwr_enable,
output reg iso_en
);
always @(posedge clk) begin
if (rst_n) begin
pwr_enable <= 1'b1;
iso_en <= 1'b0;
end else begin
if (sleep_req) begin
iso_en <= 1'b1;
pwr_enable <= 1'b1;
...
syntax details[stderr] ion not valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:49: error: Unable to bind wire/reg/memory `rst_n' in `soc_top.pd_dsp' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:49: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:49: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_34.dut.pd_dsp' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:49: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "ion not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:49: error: Unable to bind wire/reg/memory `rst_n' in `soc_top.pd_dsp'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:49: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:49: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_34.dut.pd_dsp'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:49: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | valid in assign l-value: &(pwr_enable) |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260427_200103_669320_45d5dc__sample_3
generated.v previewmodule soc_top(
input clk,
input rst_n,
input sleep_req,
input [31:0] data_in,
output reg [31:0] data_out,
output reg pwr_enable,
output reg iso_en
);
// Instantiate submodules
aon_ctrl aon_ctrl(.clk(clk), .rst_n(rst_n), .sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
pd_dsp pd_dsp(.clk(clk), .data_in(data_in), .data_out(&data_out));
endmodule
module aon_ctrl(
input clk,
input rst_n,
input sleep_req,
output reg pwr_enable,
output reg iso_en
);
always @(posedge clk) begin
if (rst_n) begin
pwr_enable <= 1'b1;
iso_en <= 1'b0;
end else begin
if (sleep_req) begin
iso_en <= 1'b1;
pwr_enable <= 1'b1;
...
syntax details[stderr] valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `soc_top.pd_dsp' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:49: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `tb_task_34.dut.pd_dsp' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:49: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `soc_top.pd_dsp'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:49: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `tb_task_34.dut.pd_dsp'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:49: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260427_200103_669320_45d5dc__sample_4
generated.v previewmodule soc_top(
input clk,
input rst_n,
input sleep_req,
input [31:0] data_in,
output reg [31:0] data_out,
output reg pwr_enable,
output reg iso_en
);
// Instantiate submodules
aon_ctrl aon_ctrl(.clk(clk), .rst_n(rst_n), .sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
pd_dsp pd_dsp(.clk(clk), .rst_n(rst_n), .data_in(data_in), .data_out(&data_out));
endmodule
module aon_ctrl(
input clk,
input rst_n,
input sleep_req,
output reg pwr_enable,
output reg iso_en
);
always @(posedge clk) begin
if (rst_n) begin
pwr_enable <= 1'b1;
iso_en <= 1'b0;
end else begin
if (sleep_req) begin
iso_en <= 1'b1;
pwr_enable <= 1'b1;
...
syntax details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:13: : Port 4 (data_out) of pd_dsp is connected to &(data_out) 3 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:13: : Port 4 (data_out) of pd_dsp is connected to &(data_out) 3 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/generated.v:13: : Port 4 (data_out) of pd_dsp is connected to &(data_out)\n3 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_4/functional/generated.v:13: : Port 4 (data_out) of pd_dsp is connected to &(data_out)\n3 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_5/generated.v:49: syntax error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260427_200103_669320_45d5dc__sample_5
generated.v previewmodule soc_top(
input clk,
input rst_n,
input sleep_req,
input [31:0] data_in,
output reg [31:0] data_out,
output reg pwr_enable,
output reg iso_en
);
// Instantiate submodules
aon_ctrl aon_ctrl(.clk(clk), .rst_n(rst_n), .sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
pd_dsp pd_dsp(.clk(clk), .data_in(data_in), .data_out(&data_out));
endmodule
module aon_ctrl(
input clk,
input rst_n,
input sleep_req,
output reg pwr_enable,
output reg iso_en
);
always @(posedge clk) begin
if (rst_n) begin
pwr_enable <= 1'b1;
iso_en <= 1'b0;
end else begin
if (sleep_req) begin
iso_en <= 1'b1;
pwr_enable <= 1'b1;
...
syntax details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_5/generated.v:49: syntax error /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_5/generated.v:49: error: Malformed conditional expression. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:49: syntax error /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:49: error: Malformed conditional expression. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_5/generated.v:49: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_5/generated.v:49: error: Malformed conditional expression.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:49: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:49: error: Malformed conditional expression.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | valid in assign l-value: &(pwr_enable) |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260427_200103_669320_45d5dc__sample_6
generated.v previewmodule soc_top(
input clk,
input rst_n,
input sleep_req,
input [31:0] data_in,
output reg [31:0] data_out,
output reg pwr_enable,
output reg iso_en
);
// Instantiate submodules
aon_ctrl aon_ctrl(.clk(clk), .rst_n(rst_n), .sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
pd_dsp pd_dsp(.clk(clk), .data_in(data_in), .data_out(&data_out));
endmodule
module aon_ctrl(
input clk,
input rst_n,
input sleep_req,
output reg pwr_enable,
output reg iso_en
);
always @(posedge clk) begin
if (rst_n) begin
pwr_enable <= 1'b1;
iso_en <= 1'b0;
end else begin
if (sleep_req) begin
iso_en <= 1'b1;
pwr_enable <= 1'b1;
...
syntax details[stderr] valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `soc_top.pd_dsp' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:49: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `tb_task_34.dut.pd_dsp' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:49: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `soc_top.pd_dsp'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:49: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `tb_task_34.dut.pd_dsp'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:49: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260427_200103_669320_45d5dc__sample_7
generated.v previewmodule soc_top(
input clk,
input rst_n,
input sleep_req,
input [31:0] data_in,
output reg [31:0] data_out,
output reg pwr_enable,
output reg iso_en
);
// Instantiate submodules
aon_ctrl aon_ctrl(.clk(clk), .rst_n(rst_n), .sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
pd_dsp pd_dsp(.clk(clk), .data_in(data_in), .data_out(&data_out));
endmodule
module aon_ctrl(
input clk,
input rst_n,
input sleep_req,
output reg pwr_enable,
output reg iso_en
);
always @(posedge clk) begin
if (rst_n) begin
pwr_enable <= 1'b1;
iso_en <= 1'b0;
end else begin
if (sleep_req) begin
iso_en <= 1'b1;
pwr_enable <= 1'b1;
...
syntax details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 3 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 3 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n3 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n3 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | valid in assign l-value: &(pwr_enable) |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260427_200103_669320_45d5dc__sample_8
generated.v previewmodule soc_top(
input clk,
input rst_n,
input sleep_req,
input [31:0] data_in,
output reg [31:0] data_out,
output reg pwr_enable,
output reg iso_en
);
// Instantiate submodules
aon_ctrl aon_ctrl(.clk(clk), .rst_n(rst_n), .sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
pd_dsp pd_dsp(.clk(clk), .data_in(data_in), .data_out(&data_out));
endmodule
module aon_ctrl(
input clk,
input rst_n,
input sleep_req,
output reg pwr_enable,
output reg iso_en
);
always @(posedge clk) begin
if (rst_n) begin
pwr_enable <= 1'b1;
iso_en <= 1'b0;
end else begin
if (sleep_req) begin
iso_en <= 1'b1;
pwr_enable <= 1'b1;
...
syntax details[stderr] valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `soc_top.pd_dsp' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:49: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `tb_task_34.dut.pd_dsp' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:49: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `soc_top.pd_dsp'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:49: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:49: error: Unable to bind wire/reg/memory `data_in_valid' in `tb_task_34.dut.pd_dsp'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:49: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | bind wire/reg/memory `rst_n' in `soc_top.aon_ctrl' |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260427_200103_669320_45d5dc__sample_9
generated.v previewmodule soc_top(
input clk,
input rst_n,
input sleep_req,
input [31:0] data_in,
output reg [31:0] data_out,
output reg pwr_enable,
output reg iso_en
);
// Instantiate submodules
aon_ctrl aon_ctrl(.sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
pd_dsp pd_dsp(.clk(clk), .rst_n(rst_n), .data_in(data_in), .data_out(&data_out));
endmodule
module aon_ctrl(
input sleep_req,
output reg pwr_enable,
output reg iso_en
);
always @(posedge clk) begin
if (rst_n) begin
pwr_enable <= 1'b1;
iso_en <= 1'b0;
end else begin
if (sleep_req) begin
iso_en <= 1'b1;
pwr_enable <= 1'b1;
end else begin
iso_en <= 1'b0;
...
syntax details[stderr] bind wire/reg/memory `rst_n' in `soc_top.aon_ctrl' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:24: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:13: : Port 4 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:24: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_34.dut.aon_ctrl' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:24: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:13: : Port 4 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": " bind wire/reg/memory `rst_n' in `soc_top.aon_ctrl'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:24: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/generated.v:13: : Port 4 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:24: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_34.dut.aon_ctrl'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:24: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:13: : Port 4 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | lid in assign l-value: &(pwr_enable) |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260427_200103_669320_45d5dc__sample_10
generated.v previewmodule soc_top(
input clk,
input rst_n,
input sleep_req,
input [31:0] data_in,
output reg [31:0] data_out,
output reg pwr_enable,
output reg iso_en
);
// Instantiate submodules
aon_ctrl aon_ctrl(.clk(clk), .rst_n(rst_n), .sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
pd_dsp pd_dsp(.clk(clk), .data_in(data_in), .data_out(&data_out));
endmodule
module aon_ctrl(
input clk,
input rst_n,
input sleep_req,
output reg pwr_enable,
output reg iso_en
);
always @(posedge clk) begin
if (rst_n) begin
pwr_enable <= 1'b1;
iso_en <= 1'b0;
end else begin
if (sleep_req) begin
iso_en <= 1'b1;
pwr_enable <= 1'b1;
...
syntax details[stderr] lid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:49: error: Unable to bind wire/reg/memory `rst_n' in `soc_top.pd_dsp' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:49: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:12: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:49: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_34.dut.pd_dsp' /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:49: error: Unable to elaborate condition expression. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out) /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:13: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out) 5 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "lid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:49: error: Unable to bind wire/reg/memory `rst_n' in `soc_top.pd_dsp'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:49: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:12: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:12: : Port 4 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:12: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:12: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:12: : Port 5 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:49: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_34.dut.pd_dsp'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:49: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:13: error: expression not valid in assign l-value: &(data_out)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:13: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:13: : Port 3 (data_out) of pd_dsp is connected to &(data_out)\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|