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codegemma:7b | RAG off

05_dft_testability / task_51 | scan_reset_override_reg

benchmarkilyasov
task_idilyasov/05_dft_testability/task_51
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260427_200103_669320_45d5dc

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_200103_669320_45d5dc__sample_1
generated.v preview 
module scan_reset_override_reg(
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input scan_in,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

    reg [3:0] scan_reg;
    reg rst_override;

    always @(posedge clk) begin
        if (!test_mode) begin
            if (!rst_n) begin
                data_out <= 0;
                scan_out <= 0;
                rst_override <= 1'b0;
            end else if (load_en) begin
                data_out <= data_in;
            end
        end else begin
            if (!rst_n) begin
                rst_override <= 1'b1;
            end
            if (scan_en) begin
                scan_out <= data_out[3];
                data_out <= {data_out[2:0], scan_in};
            end
...
functional details 
[stdout]
ERROR: reset did not initialize the register.
ERROR: functional reset was not restored when leaving test mode.
ERROR: functional reset no longer clears the register.
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:124: $finish called at 59000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_200103_669320_45d5dc__sample_2
generated.v preview 
module scan_reset_override_reg(
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input scan_in,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

    reg rst_sync;
    reg [3:0] data_reg;

    always @(posedge clk) begin
        if (rst_n == 0) begin
            rst_sync <= 1'b1;
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            rst_sync <= rst_n;
        end

        if (test_mode == 0) begin
            if (load_en == 1) begin
                data_reg <= data_in;
                data_out <= data_reg;
            end else begin
                data_out <= data_reg;
            end
        end else begin
...
functional details 
[stdout]
ERROR: reset did not initialize the register.
ERROR: functional load failed. Expected D, got x
ERROR: first scan shift failed before reset override check.
ERROR: test-mode reset override failed. Scan state was cleared by rst_n.
ERROR: scan shift did not continue while reset was asserted in test mode.
ERROR: functional reset was not restored when leaving test mode.
ERROR: functional load after test mode failed. Expected 6, got d
ERROR: functional reset no longer clears the register.
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:124: $finish called at 59000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__05_dft_testability__task_51/sample_3/generated.v:19: error: data_out Unable to assign to unresolved wires.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_200103_669320_45d5dc__sample_3
generated.v preview 
module scan_reset_override_reg(
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input scan_in,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

    reg rst_sync;
    reg [3:0] data_out_next;

    always @(posedge clk) begin
        if (!rst_n) begin
            rst_sync <= 1'b1;
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            rst_sync <= rst_n;
        end

        if (!test_mode) begin
            if (load_en) begin
                data_out_next <= data_in;
            end else begin
                data_out_next <= data_out;
            end
        end
...
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__05_dft_testability__task_51/sample_3/generated.v:19: error: data_out Unable to assign to unresolved wires.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__05_dft_testability__task_51/sample_3/generated.v:36: error: data_out Unable to assign to unresolved wires.
2 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__05_dft_testability__task_51/sample_3/functional/generated.v:19: error: data_out Unable to assign to unresolved wires.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__05_dft_testability__task_51/sample_3/functional/generated.v:36: error: data_out Unable to assign to unresolved wires.
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__05_dft_testability__task_51/sample_3/generated.v:19: error: data_out Unable to assign to unresolved wires.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__05_dft_testability__task_51/sample_3/generated.v:36: error: data_out Unable to assign to unresolved wires.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__05_dft_testability__task_51/sample_3/functional/generated.v:19: error: data_out Unable to assign to unresolved wires.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__05_dft_testability__task_51/sample_3/functional/generated.v:36: error: data_out Unable to assign to unresolved wires.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_200103_669320_45d5dc__sample_4
generated.v preview 
module scan_reset_override_reg(
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input scan_in,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

    reg rst_reg;
    reg [3:0] data_reg;

    always @(posedge clk) begin
        if (!rst_n) begin
            rst_reg <= 1'b0;
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            rst_reg <= rst_n;
        end

        if (!test_mode) begin
            if (load_en) begin
                data_reg <= data_in;
                data_out <= data_reg;
            end else begin
                data_out <= data_reg;
            end
        end else begin
...
functional details 
[stdout]
ERROR: reset did not initialize the register.
ERROR: functional load failed. Expected D, got x
ERROR: first scan shift failed before reset override check.
ERROR: test-mode reset override failed. Scan state was cleared by rst_n.
ERROR: scan shift did not continue while reset was asserted in test mode.
ERROR: functional reset was not restored when leaving test mode.
ERROR: functional load after test mode failed. Expected 6, got d
ERROR: functional reset no longer clears the register.
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:124: $finish called at 59000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_200103_669320_45d5dc__sample_5
generated.v preview 
module scan_reset_override_reg(
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input scan_in,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

    reg rst_reg;
    reg [3:0] data_reg;

    always @(posedge clk) begin
        if (!rst_n) begin
            rst_reg <= 1'b0;
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            rst_reg <= rst_n;
        end

        if (!test_mode) begin
            if (load_en) begin
                data_reg <= data_in;
                data_out <= data_reg;
            end else begin
                data_out <= data_reg;
            end
        end else begin
...
functional details 
[stdout]
ERROR: reset did not initialize the register.
ERROR: functional load failed. Expected D, got x
ERROR: first scan shift failed before reset override check.
ERROR: test-mode reset override failed. Scan state was cleared by rst_n.
ERROR: scan shift did not continue while reset was asserted in test mode.
ERROR: functional reset was not restored when leaving test mode.
ERROR: functional load after test mode failed. Expected 6, got d
ERROR: functional reset no longer clears the register.
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:124: $finish called at 59000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_200103_669320_45d5dc__sample_6
generated.v preview 
module scan_reset_override_reg(
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input scan_in,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

    reg rst_reg;
    reg load_reg;
    reg [3:0] data_in_reg;

    always @(posedge clk) begin
        if (!rst_n) begin
            rst_reg <= 1'b1;
            load_reg <= 1'b0;
            data_in_reg <= 4'b0;
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            if (!test_mode) begin
                if (load_en) begin
                    data_in_reg <= data_in;
                    load_reg <= 1'b0;
                end else begin
                    load_reg <= 1'b1;
                end
            end
...
functional details 
[stdout]
ERROR: reset did not initialize the register.
ERROR: functional load failed. Expected D, got 0
ERROR: first scan shift failed before reset override check.
ERROR: test-mode reset override failed. Scan state was cleared by rst_n.
ERROR: scan shift did not continue while reset was asserted in test mode.
ERROR: functional load after test mode failed. Expected 6, got 0
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:124: $finish called at 59000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_200103_669320_45d5dc__sample_7
generated.v preview 
module scan_reset_override_reg(
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input scan_in,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

    reg rst_reg;
    reg [3:0] data_reg;

    always @(posedge clk) begin
        if (rst_n == 0) begin
            rst_reg <= 1'b1;
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            rst_reg <= rst_n;
        end

        if (test_mode == 0) begin
            if (load_en == 1) begin
                data_reg <= data_in;
                data_out <= data_reg;
            end else begin
                data_out <= data_reg;
            end
        end else begin
...
functional details 
[stdout]
ERROR: reset did not initialize the register.
ERROR: functional load failed. Expected D, got x
ERROR: first scan shift failed before reset override check.
ERROR: test-mode reset override failed. Scan state was cleared by rst_n.
ERROR: scan shift did not continue while reset was asserted in test mode.
ERROR: functional reset was not restored when leaving test mode.
ERROR: functional load after test mode failed. Expected 6, got d
ERROR: functional reset no longer clears the register.
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:124: $finish called at 59000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_200103_669320_45d5dc__sample_8
generated.v preview 
module scan_reset_override_reg(
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input scan_in,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

    reg rst_sync;
    reg [3:0] data_out_reg;

    always @(posedge clk) begin
        if (!rst_n) begin
            rst_sync <= 1'b1;
            data_out_reg <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            rst_sync <= rst_n;
        end

        if (!test_mode) begin
            if (load_en) begin
                data_out_reg <= data_in;
            end
            data_out <= data_out_reg;
        end else begin
            if (scan_en) begin
                scan_out <= data_out_reg[3];
...
functional details 
[stdout]
ERROR: reset did not initialize the register.
ERROR: functional load failed. Expected D, got 0
ERROR: first scan shift failed before reset override check.
ERROR: test-mode reset override failed. Scan state was cleared by rst_n.
ERROR: scan shift did not continue while reset was asserted in test mode.
ERROR: functional reset was not restored when leaving test mode.
ERROR: functional load after test mode failed. Expected 6, got 5
ERROR: functional reset no longer clears the register.
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:124: $finish called at 59000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_200103_669320_45d5dc__sample_9
generated.v preview 
module scan_reset_override_reg(
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input scan_in,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

    reg rst_reg;
    reg load_reg;
    reg [3:0] data_in_reg;

    always @(posedge clk) begin
        if (!rst_n) begin
            rst_reg <= 1'b1;
            load_reg <= 1'b0;
            data_in_reg <= 4'b0;
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            if (!test_mode) begin
                if (load_en) begin
                    data_in_reg <= data_in;
                    load_reg <= 1'b0;
                end else begin
                    load_reg <= 1'b1;
                end
            end
...
functional details 
[stdout]
ERROR: reset did not initialize the register.
ERROR: functional load failed. Expected D, got 0
ERROR: first scan shift failed before reset override check.
ERROR: test-mode reset override failed. Scan state was cleared by rst_n.
ERROR: scan shift did not continue while reset was asserted in test mode.
ERROR: functional load after test mode failed. Expected 6, got 0
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:124: $finish called at 59000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_200103_669320_45d5dc__sample_10
generated.v preview 
module scan_reset_override_reg(
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input scan_in,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

    reg rst_reg;
    reg load_reg;
    reg [3:0] data_in_reg;

    always @(posedge clk) begin
        if (!rst_n) begin
            rst_reg <= 1'b1;
            load_reg <= 1'b0;
            data_in_reg <= 4'b0;
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            if (!test_mode) begin
                if (load_en) begin
                    data_in_reg <= data_in;
                    load_reg <= 1'b0;
                end else begin
                    load_reg <= 1'b1;
                end
            end
...
functional details 
[stdout]
ERROR: reset did not initialize the register.
ERROR: functional load failed. Expected D, got 0
ERROR: first scan shift failed before reset override check.
ERROR: test-mode reset override failed. Scan state was cleared by rst_n.
ERROR: scan shift did not continue while reset was asserted in test mode.
ERROR: functional load after test mode failed. Expected 6, got 0
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:124: $finish called at 59000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset did not initialize the register.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}