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codegemma:7b | RAG off

06_reset_domain_crossing / task_63 | delayed_reset_release

benchmarkilyasov
task_idilyasov/06_reset_domain_crossing/task_63
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260427_200103_669320_45d5dc

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260427_200103_669320_45d5dc__sample_1
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output reg srst_n,
    output reg init_pulse
);

    reg rst_sync;
    reg rst_done;
    reg rst_count;

    always @(posedge clk) begin
        if (arst_n == 0) begin
            srst_n <= 0;
            rst_sync <= 0;
            rst_done <= 0;
            rst_count <= 0;
            init_pulse <= 1;
        end else if (!rst_sync) begin
            rst_sync <= 1;
        end else if (!rst_done) begin
            rst_done <= 1;
        end else if (rst_count < release_delay) begin
            srst_n <= 0;
            rst_count <= rst_count + 1;
            init_pulse <= 0;
        end else begin
            srst_n <= 1;
        end
    end
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset released before the extra delay window started.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260427_200103_669320_45d5dc__sample_2
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output reg srst_n,
    output reg init_pulse
);

    reg rst_sync;
    reg rst_sync_next;
    reg [1:0] count;

    always @(posedge clk) begin
        if (arst_n == 0) begin
            srst_n <= 0;
            init_pulse <= 1;
            count <= 0;
        end else begin
            rst_sync_next <= rst_sync & arst_n;
            if (rst_sync_next == 0) begin
                srst_n <= 1'b0;
                count <= count + 1;
            end
            if (count > release_delay) begin
                srst_n <= 1'b1;
                init_pulse <= 0;
            end
        end
        rst_sync <= rst_sync_next;
    end

endmodule
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: asynchronous reassertion failed.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
ERROR: delay=0 init_pulse lasted too long.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260427_200103_669320_45d5dc__sample_3
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output reg srst_n,
    output reg init_pulse
);

    reg rst_sync;
    reg rst_sync_next;
    reg [2:0] count;

    always @(posedge clk) begin
        if (arst_n == 0) begin
            srst_n <= 0;
            init_pulse <= 1;
            count <= 0;
        end else begin
            rst_sync_next <= arst_n;
        end

        rst_sync <= rst_sync_next;

        if (rst_sync == 1'b0 && rst_sync_next == 1'b1) begin
            count <= count + 1;
        end

        if (count[2] == 1'b1) begin
            srst_n <= 1'b0;
        end

        if (count[3] == 1'b1) begin
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: asynchronous reassertion failed.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
ERROR: delay=0 init_pulse lasted too long.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260427_200103_669320_45d5dc__sample_4
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output reg srst_n,
    output reg init_pulse
);

    reg rst_sync;
    reg rst_done;
    reg rst_count;

    always @(posedge clk) begin
        if (arst_n == 0) begin
            srst_n <= 0;
            rst_sync <= 0;
            rst_done <= 0;
            rst_count <= 0;
            init_pulse <= 1;
        end else if (rst_sync == 0) begin
            rst_sync <= 1;
        end else if (rst_done == 0) begin
            rst_done <= 1;
        end else if (rst_count < release_delay) begin
            rst_count <= rst_count + 1;
            srst_n <= 0;
            init_pulse <= 0;
        end else begin
            srst_n <= 1;
            init_pulse <= 0;
        end
    end
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset released before the extra delay window started.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260427_200103_669320_45d5dc__sample_5
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output reg srst_n,
    output reg init_pulse
);

    reg rst_sync;
    reg rst_done;
    reg rst_count;

    always @(posedge clk) begin
        if (arst_n == 0) begin
            srst_n <= 0;
            rst_sync <= 0;
            rst_done <= 0;
            rst_count <= 0;
            init_pulse <= 1;
        end else if (!rst_sync) begin
            rst_sync <= 1;
        end else if (!rst_done) begin
            rst_done <= 1;
        end else if (rst_count < release_delay) begin
            srst_n <= 0;
            rst_count <= rst_count + 1;
            init_pulse <= 0;
        end else begin
            srst_n <= 1;
        end
    end
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset released before the extra delay window started.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260427_200103_669320_45d5dc__sample_6
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output reg srst_n,
    output reg init_pulse
);

    reg rst_sync;
    reg rst_done;
    reg rst_count;

    always @(posedge clk) begin
        if (arst_n == 0) begin
            srst_n <= 0;
            rst_sync <= 0;
            rst_done <= 0;
            rst_count <= 0;
            init_pulse <= 1;
        end else if (rst_sync == 0) begin
            rst_sync <= 1;
        end else if (rst_done == 0) begin
            rst_done <= 1;
        end else if (rst_count < release_delay) begin
            rst_count <= rst_count + 1;
            srst_n <= 0;
            init_pulse <= 0;
        end else begin
            srst_n <= 1;
            init_pulse <= 0;
        end
    end
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset released before the extra delay window started.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260427_200103_669320_45d5dc__sample_7
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output reg srst_n,
    output reg init_pulse
);

    reg rst_sync;
    reg rst_done;
    reg rst_count;

    always @(posedge clk) begin
        if (!arst_n) begin
            srst_n <= 0;
            rst_sync <= 0;
            rst_done <= 0;
            rst_count <= 0;
            init_pulse <= 1;
        end else if (!rst_sync) begin
            srst_n <= 1'b0;
            rst_sync <= 1;
            init_pulse <= 0;
        end else if (!rst_done) begin
            rst_done <= 1;
            rst_count <= 0;
        end else if (rst_count < release_delay) begin
            rst_count <= rst_count + 1;
            srst_n <= 1'b0;
        end else begin
            srst_n <= 1'b1;
        end
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260427_200103_669320_45d5dc__sample_8
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output reg srst_n,
    output reg init_pulse
);

    reg rst_sync;
    reg rst_sync_next;
    reg [3:0] release_counter;

    always @(posedge clk) begin
        if (arst_n == 0) begin
            srst_n <= 0;
            release_counter <= 0;
            init_pulse <= 1;
        end else begin
            rst_sync_next <= arst_n;
        end

        rst_sync <= rst_sync_next;

        if (rst_sync == 1'b0) begin
            srst_n <= 1'b0;
        end

        if (rst_sync == 1'b1 && srst_n == 1'b0) begin
            release_counter <= release_counter + 1;
        end

        if (release_counter > release_delay) begin
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: asynchronous reassertion failed.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260427_200103_669320_45d5dc__sample_9
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output reg srst_n,
    output reg init_pulse
);

    reg rst_sync;
    reg rst_done;
    reg rst_count;

    always @(posedge clk) begin
        if (arst_n == 0) begin
            srst_n <= 0;
            rst_sync <= 0;
            rst_done <= 0;
            rst_count <= 0;
            init_pulse <= 1;
        end else if (!rst_sync) begin
            rst_sync <= 1;
        end else if (!rst_done) begin
            rst_done <= 1;
        end else if (rst_count < release_delay) begin
            rst_count <= rst_count + 1;
            srst_n <= 0;
            init_pulse <= 0;
        end else begin
            srst_n <= 1;
            init_pulse <= 0;
        end
    end
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset released before the extra delay window started.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: delay=0 still requires the base synchronizer and should stay low after one edge.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260427_200103_669320_45d5dc__sample_10
generated.v preview 
module delayed_reset_release(
    input clk,
    input arst_n,
    input [1:0] release_delay,
    output reg srst_n,
    output reg init_pulse
);

    reg rst_sync;
    reg rst_hold;
    reg rst_done;
    reg rst_init;

    always @(posedge clk) begin
        if (!arst_n) begin
            srst_n <= 0;
            rst_sync <= 0;
            rst_hold <= 0;
            rst_done <= 0;
            rst_init <= 1;
        end else if (!rst_sync) begin
            rst_sync <= 1;
        end else if (!rst_hold) begin
            rst_hold <= 1;
        end else if (!rst_done) begin
            rst_done <= 1;
            init_pulse <= 1;
        end else if (release_delay > 0) begin
            if (release_delay == 1) begin
                srst_n <= 1;
            end else begin
                rst_hold <= 0;
...
functional details 
[stdout]
ERROR: outputs were not properly reset.
ERROR: reset released before the extra delay window started.
ERROR: extra hold cycle 1 failed.
ERROR: extra hold cycle 2 failed.
ERROR: reset did not release with a one-cycle init pulse after the full delay.
ERROR: init_pulse was not exactly one cycle wide.
ERROR: asynchronous reassertion failed.
ERROR: delay=0 did not release immediately after the base synchronizer completed.
ERROR: delay=0 init_pulse lasted too long.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}