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codegemma:7b | RAG off

07_csr_register_map_generation / task_72 | axil_sensor_csr

benchmarkilyasov
task_idilyasov/07_csr_register_map_generation/task_72
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260427_200103_669320_45d5dc

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:44: syntax error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_200103_669320_45d5dc__sample_1
generated.v preview 
module axil_sensor_csr(
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output awready,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output wready,
    output [1:0] bresp,
    output bvalid,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output arready,
    output [31:0] rdata,
    output [1:0] rresp,
    output rvalid,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output block_enable,
    output [7:0] gain,
    output kick_pulse,
    output irq_sticky
);

    // Register variables
    reg [31:0] ctrl_reg;
    reg [31:0] status_reg;
...
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:44: syntax error
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:46: syntax error
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:48: syntax error
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:48: error: Malformed conditional expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:46: error: Malformed conditional expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:44: error: Malformed conditional expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:55: syntax error
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:57: syntax error
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:57: error: Malformed conditional expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:55: error: Malformed conditional expression.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:44: syntax error
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:46: syntax error
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:48: syntax error
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:48: error: Malformed conditional expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:46: error: Malformed conditional expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:44: error: Malformed conditional expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:55: syntax error
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:57: syntax error
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:57: error: Malformed conditional expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:55: error: Malformed conditional expression.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:44: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:46: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:48: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:48: error: Malformed conditional expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:46: error: Malformed conditional expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:44: error: Malformed conditional expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:55: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:57: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:57: error: Malformed conditional expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:55: error: Malformed conditional expression.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:44: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:46: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:48: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:48: error: Malformed conditional expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:46: error: Malformed conditional expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:44: error: Malformed conditional expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:55: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:57: syntax error\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:57: error: Malformed conditional expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:55: error: Malformed conditional expression.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax _task_72/sample_2/generated.v:67: error: part select ctrl[7:8] is out of order.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_200103_669320_45d5dc__sample_2
generated.v preview 
module axil_sensor_csr(
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output awready,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output wready,
    output [1:0] bresp,
    output bvalid,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output arready,
    output [31:0] rdata,
    output [1:0] rresp,
    output rvalid,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output block_enable,
    output [7:0] gain,
    output kick_pulse,
    output irq_sticky
);

    // Register variables
    reg [31:0] ctrl;
    reg [31:0] status;
...
syntax details 
[stderr]
_task_72/sample_2/generated.v:67: error: part select ctrl[7:8] is out of order.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:43: error: rdata is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:17:      : rdata is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:49: error: bresp is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:11:      : bresp is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:52: error: rresp is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:18:      : rresp is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:55: error: bvalid is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:12:      : bvalid is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:58: error: rvalid is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:19:      : rvalid is declared here as wire.
6 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:67: error: part select ctrl[7:8] is out of order.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:43: error: rdata is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:17:      : rdata is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:49: error: bresp is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:11:      : bresp is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:52: error: rresp is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:18:      : rresp is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:55: error: bvalid is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:12:      : bvalid is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:58: error: rvalid is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:19:      : rvalid is declared here as wire.
6 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "_task_72/sample_2/generated.v:67: error: part select ctrl[7:8] is out of order.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:43: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:17:      : rdata is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:49: error: bresp is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:11:      : bresp is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:52: error: rresp is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:18:      : rresp is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:55: error: bvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:12:      : bvalid is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:58: error: rvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:19:      : rvalid is declared here as wire.\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:67: error: part select ctrl[7:8] is out of order.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:43: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:17:      : rdata is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:49: error: bresp is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:11:      : bresp is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:52: error: rresp is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:18:      : rresp is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:55: error: bvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:12:      : bvalid is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:58: error: rvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:19:      : rvalid is declared here as wire.\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:47: error: rdata is not a valid l-value in axil_sensor_csr.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_200103_669320_45d5dc__sample_3
generated.v preview 
module axil_sensor_csr(
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output awready,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output wready,
    output [1:0] bresp,
    output bvalid,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output arready,
    output [31:0] rdata,
    output [1:0] rresp,
    output rvalid,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output block_enable,
    output [7:0] gain,
    output kick_pulse,
    output irq_sticky
);

    // Register variables
    reg [31:0] ctrl_reg;
    reg [31:0] status_reg;
...
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:47: error: rdata is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:17:      : rdata is declared here as wire.
1 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:47: error: rdata is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:17:      : rdata is declared here as wire.
1 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:47: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:17:      : rdata is declared here as wire.\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:47: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:17:      : rdata is declared here as wire.\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:74: error: part select ctrl_reg[7:8] is out of order.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_200103_669320_45d5dc__sample_4
generated.v preview 
module axil_sensor_csr(
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output awready,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output wready,
    output [1:0] bresp,
    output bvalid,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output arready,
    output [31:0] rdata,
    output [1:0] rresp,
    output rvalid,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output block_enable,
    output [7:0] gain,
    output kick_pulse,
    output irq_sticky
);

    // Register variables
    reg [31:0] ctrl_reg;
    reg [31:0] status_reg;
...
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:74: error: part select ctrl_reg[7:8] is out of order.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:56: error: rdata is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:17:      : rdata is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:58: error: rdata is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:17:      : rdata is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:65: error: kick_pulse is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:25:      : kick_pulse is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:68: error: irq_sticky is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:26:      : irq_sticky is declared here as wire.
5 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:74: error: part select ctrl_reg[7:8] is out of order.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:56: error: rdata is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:17:      : rdata is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:58: error: rdata is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:17:      : rdata is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:65: error: kick_pulse is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:25:      : kick_pulse is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:68: error: irq_sticky is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:26:      : irq_sticky is declared here as wire.
5 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:74: error: part select ctrl_reg[7:8] is out of order.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:56: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:17:      : rdata is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:58: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:17:      : rdata is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:65: error: kick_pulse is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:25:      : kick_pulse is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:68: error: irq_sticky is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:26:      : irq_sticky is declared here as wire.\n5 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:74: error: part select ctrl_reg[7:8] is out of order.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:56: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:17:      : rdata is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:58: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:17:      : rdata is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:65: error: kick_pulse is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:25:      : kick_pulse is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:68: error: irq_sticky is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:26:      : irq_sticky is declared here as wire.\n5 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:44: error: rdata is not a valid l-value in axil_sensor_csr.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_200103_669320_45d5dc__sample_5
generated.v preview 
module axil_sensor_csr(
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output awready,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output wready,
    output [1:0] bresp,
    output bvalid,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output arready,
    output [31:0] rdata,
    output [1:0] rresp,
    output rvalid,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output block_enable,
    output [7:0] gain,
    output kick_pulse,
    output irq_sticky
);

    // Register variables
    reg [31:0] ctrl_reg;
    reg [31:0] status_reg;
...
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:44: error: rdata is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:17:      : rdata is declared here as wire.
1 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:44: error: rdata is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:17:      : rdata is declared here as wire.
1 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:44: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:17:      : rdata is declared here as wire.\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:44: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:17:      : rdata is declared here as wire.\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:58: error: rdata is not a valid l-value in axil_sensor_csr.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_200103_669320_45d5dc__sample_6
generated.v preview 
module axil_sensor_csr(
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output awready,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output wready,
    output [1:0] bresp,
    output bvalid,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output arready,
    output [31:0] rdata,
    output [1:0] rresp,
    output rvalid,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output block_enable,
    output [7:0] gain,
    output kick_pulse,
    output irq_sticky
);

    // Register variables
    reg [31:0] ctrl_reg;
    reg [31:0] status_reg;
...
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:58: error: rdata is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:17:      : rdata is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:60: error: rresp is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:18:      : rresp is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:61: error: rvalid is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:19:      : rvalid is declared here as wire.
3 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:58: error: rdata is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:17:      : rdata is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:60: error: rresp is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:18:      : rresp is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:61: error: rvalid is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:19:      : rvalid is declared here as wire.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:58: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:17:      : rdata is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:60: error: rresp is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:18:      : rresp is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:61: error: rvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:19:      : rvalid is declared here as wire.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:58: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:17:      : rdata is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:60: error: rresp is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:18:      : rresp is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:61: error: rvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:19:      : rvalid is declared here as wire.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax ion__task_72/sample_7/generated.v:17: : rdata is declared here as wire.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_200103_669320_45d5dc__sample_7
generated.v preview 
module axil_sensor_csr(
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output awready,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output wready,
    output [1:0] bresp,
    output bvalid,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output arready,
    output [31:0] rdata,
    output [1:0] rresp,
    output rvalid,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output block_enable,
    output [7:0] gain,
    output kick_pulse,
    output irq_sticky
);

    // Register variables
    reg [31:0] ctrl;
    reg [31:0] status;
...
syntax details 
[stderr]
ion__task_72/sample_7/generated.v:17:      : rdata is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:42: error: rresp is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:18:      : rresp is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:43: error: rvalid is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:19:      : rvalid is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:51: error: bresp is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:11:      : bresp is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:52: error: bvalid is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:12:      : bvalid is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:54: error: awready is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:6:      : awready is declared here as wire.
6 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:41: error: rdata is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:17:      : rdata is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:42: error: rresp is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:18:      : rresp is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:43: error: rvalid is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:19:      : rvalid is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:51: error: bresp is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:11:      : bresp is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:52: error: bvalid is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:12:      : bvalid is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:54: error: awready is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:6:      : awready is declared here as wire.
6 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "ion__task_72/sample_7/generated.v:17:      : rdata is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:42: error: rresp is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:18:      : rresp is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:43: error: rvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:19:      : rvalid is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:51: error: bresp is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:11:      : bresp is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:52: error: bvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:12:      : bvalid is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:54: error: awready is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:6:      : awready is declared here as wire.\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:41: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:17:      : rdata is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:42: error: rresp is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:18:      : rresp is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:43: error: rvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:19:      : rvalid is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:51: error: bresp is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:11:      : bresp is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:52: error: bvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:12:      : bvalid is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:54: error: awready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:6:      : awready is declared here as wire.\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260427_200103_669320_45d5dc failed failed failed skipped failed extract No module/endmodule block found in model response
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_200103_669320_45d5dc__sample_8
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "extract",
    "code": "extract.no_verilog_found",
    "message": "No module/endmodule block found in model response",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": false,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:53: error: block_enable is not a valid l-value in axil_sensor_csr.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_200103_669320_45d5dc__sample_9
generated.v preview 
module axil_sensor_csr(
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output awready,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output wready,
    output [1:0] bresp,
    output bvalid,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output arready,
    output [31:0] rdata,
    output [1:0] rresp,
    output rvalid,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output block_enable,
    output [7:0] gain,
    output kick_pulse,
    output irq_sticky
);

    // Register variables
    reg [31:0] ctrl_reg;
    reg [31:0] status_reg;
...
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:53: error: block_enable is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:23:      : block_enable is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:54: error: gain is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:24:      : gain is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:55: error: kick_pulse is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:25:      : kick_pulse is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:56: error: irq_sticky is not a valid l-value in axil_sensor_csr.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:26:      : irq_sticky is declared here as wire.
4 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:53: error: block_enable is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:23:      : block_enable is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:54: error: gain is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:24:      : gain is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:55: error: kick_pulse is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:25:      : kick_pulse is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:56: error: irq_sticky is not a valid l-value in tb_task_72.dut.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:26:      : irq_sticky is declared here as wire.
4 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:53: error: block_enable is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:23:      : block_enable is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:54: error: gain is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:24:      : gain is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:55: error: kick_pulse is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:25:      : kick_pulse is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:56: error: irq_sticky is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:26:      : irq_sticky is declared here as wire.\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:53: error: block_enable is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:23:      : block_enable is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:54: error: gain is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:24:      : gain is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:55: error: kick_pulse is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:25:      : kick_pulse is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:56: error: irq_sticky is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:26:      : irq_sticky is declared here as wire.\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260427_200103_669320_45d5dc ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_200103_669320_45d5dc__sample_10
generated.v preview 
module axil_sensor_csr(
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output awready,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output wready,
    output [1:0] bresp,
    output bvalid,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output arready,
    output [31:0] rdata,
    output [1:0] rresp,
    output rvalid,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output block_enable,
    output [7:0] gain,
    output kick_pulse,
    output irq_sticky
);

    // ... Register definitions and logic here ...

endmodule
functional details 
[stdout]
ERROR: reset values are incorrect.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL bit 0 failed.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: STATUS read without IRQ bit set returned wrong value. Got zzzzzzzz
ERROR: irq_evt did not set irq_sticky.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: STATUS read with IRQ bit set returned wrong value. Got zzzzzzzz
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: writing 0 incorrectly cleared irq_sticky.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: W1C clear of irq_sticky failed.
ERROR: AXI-Lite write channel was not ready for CMD write.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: kick_pulse did not assert on CMD write.
ERROR: kick_pulse lasted longer than one cycle.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: CMD register should read as zero. Got zzzzzzzz
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
OpenLane failed: 2
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.failed",
    "message": "OpenLane failed: 2",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}