11_side_channel_constant_time / task_110 | consttime_word_compare
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_1/generated.v:20: error: match Unable to assign to unresolved wires. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__11_side_channel_constant_time__task_110\samples\run_20260427_200103_669320_45d5dc__sample_1
generated.v previewmodule consttime_word_compare(
input clk,
input rst_n,
input start,
input [31:0] lhs,
input [31:0] rhs,
output reg busy,
output reg done,
output reg match
);
reg [31:0] lhs_reg, rhs_reg;
reg [3:0] comparison_stage;
reg match_reg;
always @(posedge clk) begin
if (!rst_n) begin
busy <= 0;
done <= 0;
match <= 0;
comparison_stage <= 0;
lhs_reg <= 0;
rhs_reg <= 0;
end else if (!busy) begin
if (start) begin
busy <= 1;
lhs_reg <= lhs;
rhs_reg <= rhs;
comparison_stage <= 0;
end
end else begin
if (comparison_stage == 4) begin
...
syntax details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_1/generated.v:20: error: match Unable to assign to unresolved wires. 1 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_1/functional/generated.v:20: error: match Unable to assign to unresolved wires. 1 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_1/generated.v:20: error: match Unable to assign to unresolved wires.\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_1/functional/generated.v:20: error: match Unable to assign to unresolved wires.\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_2/generated.v:20: error: match Unable to assign to unresolved wires. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__11_side_channel_constant_time__task_110\samples\run_20260427_200103_669320_45d5dc__sample_2
generated.v previewmodule consttime_word_compare(
input clk,
input rst_n,
input start,
input [31:0] lhs,
input [31:0] rhs,
output reg busy,
output reg done,
output reg match
);
reg [31:0] lhs_reg, rhs_reg;
reg [3:0] cycle_cnt;
reg match_reg;
always @(posedge clk) begin
if (!rst_n) begin
busy <= 0;
done <= 0;
match <= 0;
cycle_cnt <= 0;
lhs_reg <= 0;
rhs_reg <= 0;
match_reg <= 0;
end else begin
if (!busy && start) begin
busy <= 1;
lhs_reg <= lhs;
rhs_reg <= rhs;
cycle_cnt <= 0;
match_reg <= 0;
end
...
syntax details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_2/generated.v:20: error: match Unable to assign to unresolved wires. 1 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_2/functional/generated.v:20: error: match Unable to assign to unresolved wires. 1 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_2/generated.v:20: error: match Unable to assign to unresolved wires.\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_2/functional/generated.v:20: error: match Unable to assign to unresolved wires.\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_3/generated.v:20: error: match Unable to assign to unresolved wires. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__11_side_channel_constant_time__task_110\samples\run_20260427_200103_669320_45d5dc__sample_3
generated.v previewmodule consttime_word_compare(
input clk,
input rst_n,
input start,
input [31:0] lhs,
input [31:0] rhs,
output reg busy,
output reg done,
output reg match
);
reg [31:0] lhs_reg, rhs_reg;
reg [3:0] cycle_count;
reg match_reg;
always @(posedge clk) begin
if (!rst_n) begin
busy <= 0;
done <= 0;
match <= 0;
cycle_count <= 0;
lhs_reg <= 0;
rhs_reg <= 0;
match_reg <= 0;
end else begin
if (!busy && start) begin
busy <= 1;
lhs_reg <= lhs;
rhs_reg <= rhs;
cycle_count <= 0;
match_reg <= 0;
end
...
syntax details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_3/generated.v:20: error: match Unable to assign to unresolved wires. 1 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_3/functional/generated.v:20: error: match Unable to assign to unresolved wires. 1 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_3/generated.v:20: error: match Unable to assign to unresolved wires.\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_3/functional/generated.v:20: error: match Unable to assign to unresolved wires.\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_200103_669320_45d5dc | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR (reset asserted): busy=x expected=0 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__11_side_channel_constant_time__task_110\samples\run_20260427_200103_669320_45d5dc__sample_4
generated.v previewmodule consttime_word_compare(
input clk,
input rst_n,
input start,
input [31:0] lhs,
input [31:0] rhs,
output reg busy,
output reg done,
output reg match
);
reg [31:0] lhs_reg, rhs_reg;
reg [3:0] compare_cycle;
reg match_reg;
always @(posedge clk) begin
if (!rst_n) begin
busy <= 0;
done <= 0;
match <= 0;
compare_cycle <= 0;
lhs_reg <= 0;
rhs_reg <= 0;
end else if (!busy) begin
if (start) begin
busy <= 1;
lhs_reg <= lhs;
rhs_reg <= rhs;
compare_cycle <= 1;
end
end else begin
if (compare_cycle < 4) begin
...
functional details[stdout] ERROR (reset asserted): busy=x expected=0 ERROR (reset asserted): done=x expected=0 ERROR (reset asserted): match=x expected=0 ERROR (equal words): busy=0 expected=1 ERROR (equal words): match=x expected=1 ERROR (return to idle): done=1 expected=0 ERROR (return to idle): match=x expected=0 ERROR (accept request): done=1 expected=0 ERROR (accept request): match=x expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): match=x expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): match=x expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): match=x expected=0 ERROR (mismatch byte0): busy=0 expected=1 ERROR (return to idle): done=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): busy=0 expected=1 ERROR (return to idle): done=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (ignore busy start): done=1 expected=0 ERROR (ignore busy start progress): done=1 expected=0 ERROR (ignore busy start progress): done=1 expected=0 ERROR (ignore busy start result): busy=0 expected=1 ERROR (ignore busy start result): match=0 expected=1 ERROR (idle after ignored start): done=1 expected=0 ERROR (accept request): done=1 expected=0 ... synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR (reset asserted): busy=x expected=0",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_200103_669320_45d5dc | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR (reset asserted): busy=x expected=0 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__11_side_channel_constant_time__task_110\samples\run_20260427_200103_669320_45d5dc__sample_5
generated.v previewmodule consttime_word_compare(
input clk,
input rst_n,
input start,
input [31:0] lhs,
input [31:0] rhs,
output reg busy,
output reg done,
output reg match
);
reg [31:0] lhs_reg, rhs_reg;
reg [3:0] compare_cycle;
reg match_reg;
always @(posedge clk) begin
if (!rst_n) begin
busy <= 0;
done <= 0;
match <= 0;
compare_cycle <= 0;
lhs_reg <= 0;
rhs_reg <= 0;
end else if (!busy) begin
if (start) begin
busy <= 1;
lhs_reg <= lhs;
rhs_reg <= rhs;
compare_cycle <= 0;
end
end else begin
if (compare_cycle == 4) begin
...
functional details[stdout] ERROR (reset asserted): busy=x expected=0 ERROR (reset asserted): done=x expected=0 ERROR (reset asserted): match=x expected=0 ERROR (equal words): done=0 expected=1 ERROR (equal words): match=0 expected=1 ERROR (return to idle): done=1 expected=0 ERROR (return to idle): match=x expected=0 ERROR (accept request): done=1 expected=0 ERROR (accept request): match=x expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): match=x expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): match=x expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): match=x expected=0 ERROR (mismatch byte0): match=x expected=0 ERROR (return to idle): done=1 expected=0 ERROR (return to idle): match=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (accept request): match=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): match=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): match=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): match=1 expected=0 ERROR (mismatch byte2): match=1 expected=0 ERROR (return to idle): done=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (ignore busy start): done=1 expected=0 ERROR (ignore busy start progress): done=1 expected=0 ... synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR (reset asserted): busy=x expected=0",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260427_200103_669320_45d5dc | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR (reset asserted): busy=x expected=0 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__11_side_channel_constant_time__task_110\samples\run_20260427_200103_669320_45d5dc__sample_6
generated.v previewmodule consttime_word_compare(
input clk,
input rst_n,
input start,
input [31:0] lhs,
input [31:0] rhs,
output reg busy,
output reg done,
output reg match
);
reg [31:0] lhs_reg, rhs_reg;
reg [3:0] cycle_cnt;
reg match_reg;
always @(posedge clk) begin
if (!rst_n) begin
busy <= 0;
done <= 0;
match <= 0;
cycle_cnt <= 0;
lhs_reg <= 0;
rhs_reg <= 0;
end else begin
if (!busy && start) begin
busy <= 1;
lhs_reg <= lhs;
rhs_reg <= rhs;
cycle_cnt <= 0;
end
if (busy) begin
...
functional details[stdout] ERROR (reset asserted): busy=x expected=0 ERROR (reset asserted): done=x expected=0 ERROR (reset asserted): match=x expected=0 ERROR (post reset idle): match=x expected=0 ERROR (accept request): match=x expected=0 ERROR (equal words): match=x expected=0 ERROR (equal words): match=1 expected=0 ERROR (equal words): match=1 expected=0 ERROR (equal words): busy=0 expected=1 ERROR (return to idle): done=1 expected=0 ERROR (return to idle): match=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (accept request): match=1 expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): match=1 expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): busy=0 expected=1 ERROR (return to idle): done=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): match=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): match=1 expected=0 ERROR (mismatch byte2): busy=0 expected=1 ERROR (return to idle): done=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (ignore busy start): done=1 expected=0 ERROR (ignore busy start progress): done=1 expected=0 ERROR (ignore busy start progress): match=1 expected=0 ... synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR (reset asserted): busy=x expected=0",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_200103_669320_45d5dc | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR (reset asserted): busy=x expected=0 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__11_side_channel_constant_time__task_110\samples\run_20260427_200103_669320_45d5dc__sample_7
generated.v previewmodule consttime_word_compare(
input clk,
input rst_n,
input start,
input [31:0] lhs,
input [31:0] rhs,
output reg busy,
output reg done,
output reg match
);
reg [31:0] lhs_reg, rhs_reg;
reg [3:0] compare_cycle;
reg match_reg;
always @(posedge clk) begin
if (!rst_n) begin
busy <= 0;
done <= 0;
match <= 0;
compare_cycle <= 0;
lhs_reg <= 0;
rhs_reg <= 0;
end else begin
if (!busy && start) begin
busy <= 1;
lhs_reg <= lhs;
rhs_reg <= rhs;
compare_cycle <= 0;
end
if (busy) begin
...
functional details[stdout] ERROR (reset asserted): busy=x expected=0 ERROR (reset asserted): done=x expected=0 ERROR (reset asserted): match=x expected=0 ERROR (equal words): done=0 expected=1 ERROR (equal words): match=0 expected=1 ERROR (return to idle): done=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (return to idle): done=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (return to idle): done=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (ignore busy start): done=1 expected=0 ERROR (ignore busy start progress): done=1 expected=0 ERROR (ignore busy start progress): done=1 expected=0 ERROR (ignore busy start result): match=0 expected=1 ERROR (idle after ignored start): done=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (mid-transaction before reset): done=1 expected=0 ERROR (async reset clears active op): busy=1 expected=0 ERROR (async reset clears active op): done=1 expected=0 ERROR (final mismatch): done=0 expected=1 ERROR (return to idle): done=1 expected=0 TEST_FAILED /workspace/banchmarks/pashencev/11_side_channel_constant_time/task_110/tb.v:161: $finish called at 356000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR (reset asserted): busy=x expected=0",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260427_200103_669320_45d5dc | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR (reset asserted): busy=x expected=0 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__11_side_channel_constant_time__task_110\samples\run_20260427_200103_669320_45d5dc__sample_8
generated.v previewmodule consttime_word_compare(
input clk,
input rst_n,
input start,
input [31:0] lhs,
input [31:0] rhs,
output reg busy,
output reg done,
output reg match
);
reg [31:0] lhs_reg, rhs_reg;
reg [3:0] state;
reg [3:0] comparison_cycle;
always @(posedge clk) begin
if (!rst_n) begin
state <= 0;
comparison_cycle <= 0;
busy <= 0;
done <= 0;
match <= 0;
lhs_reg <= 0;
rhs_reg <= 0;
end else begin
if (!busy) begin
if (start) begin
busy <= 1;
lhs_reg <= lhs;
rhs_reg <= rhs;
state <= 1;
end
...
functional details[stdout] ERROR (reset asserted): busy=x expected=0 ERROR (reset asserted): done=x expected=0 ERROR (reset asserted): match=x expected=0 ERROR (equal words): done=0 expected=1 ERROR (equal words): match=0 expected=1 ERROR (return to idle): busy=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (accept request): match=1 expected=0 ERROR (mismatch byte0): busy=0 expected=1 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): match=1 expected=0 ERROR (mismatch byte0): busy=0 expected=1 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): match=1 expected=0 ERROR (mismatch byte0): busy=0 expected=1 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): match=1 expected=0 ERROR (mismatch byte0): busy=0 expected=1 ERROR (mismatch byte0): match=1 expected=0 ERROR (return to idle): done=1 expected=0 ERROR (return to idle): match=1 expected=0 ERROR (accept request): busy=0 expected=1 ERROR (accept request): done=1 expected=0 ERROR (accept request): match=1 expected=0 ERROR (mismatch byte2): busy=0 expected=1 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): match=1 expected=0 ERROR (mismatch byte2): busy=0 expected=1 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): match=1 expected=0 ERROR (mismatch byte2): busy=0 expected=1 ... synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR (reset asserted): busy=x expected=0",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260427_200103_669320_45d5dc | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR (reset asserted): busy=x expected=0 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__11_side_channel_constant_time__task_110\samples\run_20260427_200103_669320_45d5dc__sample_9
generated.v previewmodule consttime_word_compare(
input clk,
input rst_n,
input start,
input [31:0] lhs,
input [31:0] rhs,
output reg busy,
output reg done,
output reg match
);
reg [31:0] lhs_reg, rhs_reg;
reg [3:0] cycle_count;
reg match_reg;
always @(posedge clk) begin
if (!rst_n) begin
busy <= 0;
done <= 0;
match <= 0;
cycle_count <= 0;
lhs_reg <= 0;
rhs_reg <= 0;
end else begin
if (!busy && start) begin
busy <= 1;
lhs_reg <= lhs;
rhs_reg <= rhs;
cycle_count <= 0;
end
if (busy) begin
...
functional details[stdout] ERROR (reset asserted): busy=x expected=0 ERROR (reset asserted): done=x expected=0 ERROR (reset asserted): match=x expected=0 ERROR (post reset idle): match=x expected=0 ERROR (accept request): match=x expected=0 ERROR (equal words): match=x expected=0 ERROR (equal words): match=1 expected=0 ERROR (equal words): match=1 expected=0 ERROR (equal words): busy=0 expected=1 ERROR (return to idle): done=1 expected=0 ERROR (return to idle): match=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (accept request): match=1 expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): match=1 expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): done=1 expected=0 ERROR (mismatch byte0): busy=0 expected=1 ERROR (return to idle): done=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): match=1 expected=0 ERROR (mismatch byte2): done=1 expected=0 ERROR (mismatch byte2): match=1 expected=0 ERROR (mismatch byte2): busy=0 expected=1 ERROR (return to idle): done=1 expected=0 ERROR (accept request): done=1 expected=0 ERROR (ignore busy start): done=1 expected=0 ERROR (ignore busy start progress): done=1 expected=0 ERROR (ignore busy start progress): match=1 expected=0 ... synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR (reset asserted): busy=x expected=0",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | This msb expression violates the rule: ('sd31)-(cycle_count) |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__11_side_channel_constant_time__task_110\samples\run_20260427_200103_669320_45d5dc__sample_10
generated.v previewmodule consttime_word_compare(
input clk,
input rst_n,
input start,
input [31:0] lhs,
input [31:0] rhs,
output reg busy,
output reg done,
output reg match
);
reg [31:0] lhs_reg, rhs_reg;
reg [3:0] cycle_count;
reg match_reg;
always @(posedge clk) begin
if (!rst_n) begin
busy <= 0;
done <= 0;
match <= 0;
cycle_count <= 0;
lhs_reg <= 0;
rhs_reg <= 0;
match_reg <= 0;
end else begin
if (!busy && start) begin
busy <= 1;
lhs_reg <= lhs;
rhs_reg <= rhs;
cycle_count <= 0;
match_reg <= 1;
end
...
syntax details[stderr]
This msb expression violates the rule: ('sd31)-(cycle_count)
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: error: Part select expressions must be constant.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: error: Part select expressions must be constant.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: error: Part select expressions must be constant.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)
8 error(s) during elaboration.
functional details[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: Part select expressions must be constant.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: Part select expressions must be constant.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: Part select expressions must be constant.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: Part select expressions must be constant.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)
8 error(s) during elaboration.
synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "This msb expression violates the rule: ('sd31)-(cycle_count)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: error: Part select expressions must be constant.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: error: Part select expressions must be constant.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: error: Part select expressions must be constant.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)\n8 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: Part select expressions must be constant.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: Part select expressions must be constant.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: Part select expressions must be constant.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: A reference to a wire or reg (`cycle_count') is not allowed in a constant expression.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: error: Part select expressions must be constant.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/pashencev__11_side_channel_constant_time__task_110/sample_10/functional/generated.v:40: : This msb expression violates the rule: ('sd31)-(cycle_count)\n8 error(s) during elaboration.\n",
"retryable": false,
"details": {}…
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|