codegemma:7b | RAG off

12_cdv / task_121 | queue_credit_tracker

benchmarkilyasov

task_idilyasov/12_cdv/task_121

samples_total10

final_success_samples2

final_success_rate_samples20.0%

functional_pass_rate_samples100.0%

synth_pass_rate_samples20.0%

source_runsrun_20260427_200103_669320_45d5dc

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample	run	extract_ok	syntax_ok	functional_ok	openlane_ok	final_success	failure_stage	failure_reason	details
sample_1	run_20260427_200103_669320_45d5dc	ok	ok	n/a	failed	failed	synthesis	OpenLane failed: 2	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260427_200103_669320_45d5dc__sample_1 generated.v preview module queue_credit_tracker( input clk, input rst, input cfg_limit, input push, input pop, input flush, output reg count, output reg overflow_pulse, output reg underflow_pulse ); // ... endmodule synthesis details [error] OpenLane failed: 2 errors[] [ { "stage": "openlane", "code": "openlane.failed", "message": "OpenLane failed: 2", "retryable": false, "details": {} } ] outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": false, "syntax_required": true, "functional_required": false, "openlane_required": true, "final_success": false, "success": false }
sample_2	run_20260427_200103_669320_45d5dc	ok	ok	n/a	failed	failed	synthesis	OpenLane failed: 2	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260427_200103_669320_45d5dc__sample_2 generated.v preview module queue_credit_tracker( input clk, input rst, input cfg_limit, input push, input pop, input flush, output reg count, output reg overflow_pulse, output reg underflow_pulse ); // ... endmodule synthesis details [error] OpenLane failed: 2 errors[] [ { "stage": "openlane", "code": "openlane.failed", "message": "OpenLane failed: 2", "retryable": false, "details": {} } ] outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": false, "syntax_required": true, "functional_required": false, "openlane_required": true, "final_success": false, "success": false }
sample_3	run_20260427_200103_669320_45d5dc	ok	ok	n/a	failed	failed	synthesis	OpenLane failed: 2	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260427_200103_669320_45d5dc__sample_3 generated.v preview module queue_credit_tracker( input clk, input rst, input cfg_limit, input push, input pop, input flush, output reg count, output reg overflow_pulse, output reg underflow_pulse ); // ... endmodule synthesis details [error] OpenLane failed: 2 errors[] [ { "stage": "openlane", "code": "openlane.failed", "message": "OpenLane failed: 2", "retryable": false, "details": {} } ] outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": false, "syntax_required": true, "functional_required": false, "openlane_required": true, "final_success": false, "success": false }
sample_4	run_20260427_200103_669320_45d5dc	ok	ok	n/a	failed	failed	synthesis	OpenLane failed: 2	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260427_200103_669320_45d5dc__sample_4 generated.v preview module queue_credit_tracker( input clk, input rst, input cfg_limit, input push, input pop, input flush, output reg count, output reg overflow_pulse, output reg underflow_pulse ); // ... endmodule synthesis details [error] OpenLane failed: 2 errors[] [ { "stage": "openlane", "code": "openlane.failed", "message": "OpenLane failed: 2", "retryable": false, "details": {} } ] outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": false, "syntax_required": true, "functional_required": false, "openlane_required": true, "final_success": false, "success": false }
sample_5	run_20260427_200103_669320_45d5dc	ok	ok	n/a	failed	failed	synthesis	OpenLane failed: 2	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260427_200103_669320_45d5dc__sample_5 generated.v preview module queue_credit_tracker( input clk, input rst, input cfg_limit, input push, input pop, input flush, output reg count, output reg overflow_pulse, output reg underflow_pulse ); // ... endmodule synthesis details [error] OpenLane failed: 2 errors[] [ { "stage": "openlane", "code": "openlane.failed", "message": "OpenLane failed: 2", "retryable": false, "details": {} } ] outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": false, "syntax_required": true, "functional_required": false, "openlane_required": true, "final_success": false, "success": false }
sample_6	run_20260427_200103_669320_45d5dc	ok	ok	n/a	ok	ok	success	Full pipeline success	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260427_200103_669320_45d5dc__sample_6 generated.v preview module queue_credit_tracker( input clk, input rst, input cfg_limit, input push, input pop, input flush, output reg count, output reg overflow_pulse, output reg underflow_pulse ); reg [3:0] state; reg [3:0] capacity; always @(posedge clk) begin if (rst) begin state <= 0; capacity <= 0; count <= 0; overflow_pulse <= 0; underflow_pulse <= 0; end else begin if (cfg_limit != capacity) begin capacity <= cfg_limit + 1; end if (push) begin if (count < capacity - 1) begin count <= count + 1; ... synthesis details [error] None outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": true, "syntax_required": true, "functional_required": false, "openlane_required": true, "final_success": true, "success": true }
sample_7	run_20260427_200103_669320_45d5dc	ok	ok	n/a	failed	failed	synthesis	OpenLane failed: 2	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260427_200103_669320_45d5dc__sample_7 generated.v preview module queue_credit_tracker( input clk, input rst, input cfg_limit, input push, input pop, input flush, output reg count, output reg overflow_pulse, output reg underflow_pulse ); // ... endmodule synthesis details [error] OpenLane failed: 2 errors[] [ { "stage": "openlane", "code": "openlane.failed", "message": "OpenLane failed: 2", "retryable": false, "details": {} } ] outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": false, "syntax_required": true, "functional_required": false, "openlane_required": true, "final_success": false, "success": false }
sample_8	run_20260427_200103_669320_45d5dc	ok	ok	n/a	failed	failed	synthesis	OpenLane failed: 2	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260427_200103_669320_45d5dc__sample_8 generated.v preview module queue_credit_tracker( input clk, input rst, input cfg_limit, input push, input pop, input flush, output reg count, output reg overflow_pulse, output reg underflow_pulse ); // ... endmodule synthesis details [error] OpenLane failed: 2 errors[] [ { "stage": "openlane", "code": "openlane.failed", "message": "OpenLane failed: 2", "retryable": false, "details": {} } ] outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": false, "syntax_required": true, "functional_required": false, "openlane_required": true, "final_success": false, "success": false }
sample_9	run_20260427_200103_669320_45d5dc	ok	ok	n/a	ok	ok	success	Full pipeline success	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260427_200103_669320_45d5dc__sample_9 generated.v preview module queue_credit_tracker( input clk, input rst, input cfg_limit, input push, input pop, input flush, output reg count, output reg overflow_pulse, output reg underflow_pulse ); reg [3:0] queue_depth; always @(posedge clk) begin if (rst) begin count <= 0; queue_depth <= 0; end else begin if (push) begin if (queue_depth < cfg_limit) begin count <= count + 1; queue_depth <= queue_depth + 1; end else begin overflow_pulse <= 1'b1; end end else if (pop) begin if (queue_depth > 0) begin count <= count - 1; queue_depth <= queue_depth - 1; ... synthesis details [error] None outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": true, "syntax_required": true, "functional_required": false, "openlane_required": true, "final_success": true, "success": true }
sample_10	run_20260427_200103_669320_45d5dc	ok	ok	n/a	failed	failed	synthesis	OpenLane failed: 2	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260427_200103_669320_45d5dc__sample_10 generated.v preview module queue_credit_tracker( input clk, input rst, input cfg_limit, input push, input pop, input flush, output reg count, output reg overflow_pulse, output reg underflow_pulse ); // ... endmodule synthesis details [error] OpenLane failed: 2 errors[] [ { "stage": "openlane", "code": "openlane.failed", "message": "OpenLane failed: 2", "retryable": false, "details": {} } ] outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": false, "syntax_required": true, "functional_required": false, "openlane_required": true, "final_success": false, "success": false }