13_rtllm_arithmetic / task_02 | verified_adder_16bit
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260427_200103_669320_45d5dc | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260427_200103_669320_45d5dc__sample_1
generated.v previewmodule adder_16bit(
input wire [15:0] a,
input wire [15:0] b,
input wire Cin,
output wire [15:0] y,
output wire Co
);
// Instantiate 8-bit adders
adder_8bit adder0(.a(a[7:0]), .b(b[7:0]), .Cin(Cin), .y(y[7:0]), .Co(Co));
adder_8bit adder1(.a(a[15:8]), .b(b[15:8]), .Cin(Co), .y(y[15:8]), .Co(Co));
endmodule
module adder_8bit(
input wire [7:0] a,
input wire [7:0] b,
input wire Cin,
output wire [7:0] y,
output wire Co
);
// Logic for 8-bit adder
assign y = a ^ b ^ Cin;
assign Co = a & b | a & Cin | b & Cin;
endmodule
functional details[stdout] ===========Test completed with 99 / 100 failures=========== synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260427_200103_669320_45d5dc | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260427_200103_669320_45d5dc__sample_2
generated.v previewmodule adder_16bit(
input wire [15:0] a,
input wire [15:0] b,
input wire Cin,
output wire [15:0] y,
output wire Co
);
// Instantiate 8-bit adders
adder_8bit adder0(.a(a[7:0]), .b(b[7:0]), .Cin(Cin), .y(y[7:0]), .Co(Co));
adder_8bit adder1(.a(a[15:8]), .b(b[15:8]), .Cin(Co), .y(y[15:8]), .Co(Co));
endmodule
module adder_8bit(
input wire [7:0] a,
input wire [7:0] b,
input wire Cin,
output wire [7:0] y,
output wire Co
);
// Logic for 8-bit adder
assign y = a ^ b ^ Cin;
assign Co = a & b | a & Cin | b & Cin;
endmodule
functional details[stdout] ===========Test completed with 99 / 100 failures=========== synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_200103_669320_45d5dc | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260427_200103_669320_45d5dc__sample_3
generated.v previewmodule adder_16bit(
input wire [15:0] a,
input wire [15:0] b,
input wire Cin,
output wire [15:0] y,
output wire Co
);
// Instantiate 8-bit adders
adder_8bit adder0(.a(a[7:0]), .b(b[7:0]), .Cin(Cin), .y(y[7:0]), .Co(Co));
adder_8bit adder1(.a(a[15:8]), .b(b[15:8]), .Cin(Co), .y(y[15:8]), .Co(Co));
endmodule
module adder_8bit(
input wire [7:0] a,
input wire [7:0] b,
input wire Cin,
output wire [7:0] y,
output wire Co
);
// Logic for 8-bit adder
assign y = a ^ b ^ Cin;
assign Co = a & b | a & Cin | b & Cin;
endmodule
functional details[stdout] ===========Test completed with 99 / 100 failures=========== synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_200103_669320_45d5dc | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260427_200103_669320_45d5dc__sample_4
generated.v previewmodule adder_16bit(
input wire [15:0] a,
input wire [15:0] b,
input wire Cin,
output wire [15:0] y,
output wire Co
);
// Instantiate 8-bit adders
adder_8bit adder0(.a(a[7:0]), .b(b[7:0]), .Cin(Cin), .y(y[7:0]), .Co(Co));
adder_8bit adder1(.a(a[15:8]), .b(b[15:8]), .Cin(Co), .y(y[15:8]), .Co(Co));
endmodule
module adder_8bit(
input wire [7:0] a,
input wire [7:0] b,
input wire Cin,
output wire [7:0] y,
output wire Co
);
// Logic for 8-bit adder
// ...
endmodule
functional details[stdout] ===========Test completed with 100 / 100 failures=========== synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_200103_669320_45d5dc | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260427_200103_669320_45d5dc__sample_5
generated.v previewmodule adder_16bit(
input wire [15:0] a,
input wire [15:0] b,
input wire Cin,
output wire [15:0] y,
output wire Co
);
// Instantiate 8-bit adders
adder_8bit adder0(.a(a[7:0]), .b(b[7:0]), .Cin(Cin), .y(y[7:0]), .Co(Co));
adder_8bit adder1(.a(a[15:8]), .b(b[15:8]), .Cin(Co), .y(y[15:8]), .Co(Co));
endmodule
module adder_8bit(
input wire [7:0] a,
input wire [7:0] b,
input wire Cin,
output wire [7:0] y,
output wire Co
);
// Logic for 8-bit adder
assign y = a ^ b ^ Cin;
assign Co = a & b | a & Cin | b & Cin;
endmodule
functional details[stdout] ===========Test completed with 99 / 100 failures=========== synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_6/generated.v:11: error: Unresolved net/uwire Co cannot have multiple drivers. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260427_200103_669320_45d5dc__sample_6
generated.v previewmodule adder_16bit(
input logic [15:0] a,
input logic [15:0] b,
input logic Cin,
output logic [15:0] y,
output logic Co
);
// Instantiate 8-bit adders
adder8 bit_adder(.a(a[7:0]), .b(b[7:0]), .Cin(Cin), .y(y[7:0]), .Co(Co));
adder8 bit_adder2(.a(a[15:8]), .b(b[15:8]), .Cin(Co), .y(y[15:8]), .Co(Co));
endmodule
module adder8(
input logic [7:0] a,
input logic [7:0] b,
input logic Cin,
output logic [7:0] y,
output logic Co
);
// Logic for 8-bit adder
// ...
endmodule
syntax details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_6/generated.v:11: error: Unresolved net/uwire Co cannot have multiple drivers. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_6/generated.v:11: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_6/generated.v:11: : Port 5 (Co) of adder8 is connected to Co 2 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_6/functional/generated.v:11: error: Unresolved net/uwire Co cannot have multiple drivers. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_6/functional/generated.v:11: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_6/functional/generated.v:11: : Port 5 (Co) of adder8 is connected to Co 2 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_6/generated.v:11: error: Unresolved net/uwire Co cannot have multiple drivers.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_6/generated.v:11: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_6/generated.v:11: : Port 5 (Co) of adder8 is connected to Co\n2 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_6/functional/generated.v:11: error: Unresolved net/uwire Co cannot have multiple drivers.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_6/functional/generated.v:11: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_6/functional/generated.v:11: : Port 5 (Co) of adder8 is connected to Co\n2 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_200103_669320_45d5dc | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_7/generated.v:11: error: Unresolved net/uwire Co cannot have multiple drivers. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260427_200103_669320_45d5dc__sample_7
generated.v previewmodule adder_16bit(
input logic [15:0] a,
input logic [15:0] b,
input logic Cin,
output logic [15:0] y,
output logic Co
);
// Instantiate 8-bit adders
adder_8bit adder_a(a[7:0], b[7:0], Cin, y[7:0], Co);
adder_8bit adder_b(a[15:8], b[15:8], Co, y[15:8], Co);
endmodule
module adder_8bit(
input logic [7:0] a,
input logic [7:0] b,
input logic Cin,
output logic [7:0] y,
output logic Co
);
// Logic for 8-bit adder
assign y = a ^ b ^ Cin;
assign Co = a & b | a & Cin | b & Cin;
endmodule
syntax details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_7/generated.v:11: error: Unresolved net/uwire Co cannot have multiple drivers. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_7/generated.v:11: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_7/generated.v:11: : Port 5 (Co) of adder_8bit is connected to Co 2 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_7/functional/generated.v:11: error: Unresolved net/uwire Co cannot have multiple drivers. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_7/functional/generated.v:11: error: Output port expression must support continuous assignment. /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_7/functional/generated.v:11: : Port 5 (Co) of adder_8bit is connected to Co 2 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_7/generated.v:11: error: Unresolved net/uwire Co cannot have multiple drivers.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_7/generated.v:11: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_7/generated.v:11: : Port 5 (Co) of adder_8bit is connected to Co\n2 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_7/functional/generated.v:11: error: Unresolved net/uwire Co cannot have multiple drivers.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_7/functional/generated.v:11: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_02/sample_7/functional/generated.v:11: : Port 5 (Co) of adder_8bit is connected to Co\n2 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260427_200103_669320_45d5dc | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260427_200103_669320_45d5dc__sample_8
generated.v previewmodule adder_16bit(
input wire [15:0] a,
input wire [15:0] b,
input wire Cin,
output wire [15:0] y,
output wire Co
);
// Instantiate 8-bit adders
adder_8bit adder0(.a(a[7:0]), .b(b[7:0]), .Cin(Cin), .y(y[7:0]), .Co(Co));
adder_8bit adder1(.a(a[15:8]), .b(b[15:8]), .Cin(Co), .y(y[15:8]), .Co(Co));
endmodule
module adder_8bit(
input wire [7:0] a,
input wire [7:0] b,
input wire Cin,
output wire [7:0] y,
output wire Co
);
// Logic for 8-bit adder
assign y = a ^ b ^ Cin;
assign Co = a & b | a & Cin | b & Cin;
endmodule
functional details[stdout] ===========Test completed with 99 / 100 failures=========== synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260427_200103_669320_45d5dc | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260427_200103_669320_45d5dc__sample_9
generated.v previewmodule adder_16bit(
input wire [15:0] a,
input wire [15:0] b,
input wire Cin,
output wire [15:0] y,
output wire Co
);
// Instantiate 8-bit adders
adder_8bit adder0(.a(a[7:0]), .b(b[7:0]), .Cin(Cin), .y(y[7:0]), .Co(Co));
adder_8bit adder1(.a(a[15:8]), .b(b[15:8]), .Cin(Co), .y(y[15:8]), .Co(Co));
endmodule
module adder_8bit(
input wire [7:0] a,
input wire [7:0] b,
input wire Cin,
output wire [7:0] y,
output wire Co
);
// Logic for 8-bit adder
assign y = a ^ b ^ Cin;
assign Co = a & b | a & Cin | b & Cin;
endmodule
functional details[stdout] ===========Test completed with 99 / 100 failures=========== synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260427_200103_669320_45d5dc | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260427_200103_669320_45d5dc__sample_10
generated.v previewmodule adder_16bit(
input wire [15:0] a,
input wire [15:0] b,
input wire Cin,
output wire [15:0] y,
output wire Co
);
// Instantiate 8-bit adders
adder_8bit adder0(.a(a[7:0]), .b(b[7:0]), .Cin(Cin), .y(y[7:0]), .Co(Co));
adder_8bit adder1(.a(a[15:8]), .b(b[15:8]), .Cin(Co), .y(y[15:8]), .Co(Co));
endmodule
module adder_8bit(
input wire [7:0] a,
input wire [7:0] b,
input wire Cin,
output wire [7:0] y,
output wire Co
);
// Logic for 8-bit adder
assign y = a ^ b ^ Cin;
assign Co = a & b | a & Cin | b & Cin;
endmodule
functional details[stdout] ===========Test completed with 99 / 100 failures=========== synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|