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codegemma:7b | RAG off

13_rtllm_arithmetic / task_06 | verified_adder_64bit

benchmarkrtllm
task_idrtllm/13_rtllm_arithmetic/task_06
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260427_200103_669320_45d5dc

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_200103_669320_45d5dc__sample_1
generated.v preview 
module adder_pipe_64bit(
    input clk, rst_n, i_en,
    input [63:0] adda, addb,
    output reg [64:0] result,
    output reg o_en
);

    reg [63:0] r_a, r_b;
    reg [63:0] r_sum0, r_sum1, r_sum2;
    reg [63:0] r_carry0, r_carry1;

    always @(posedge clk) begin
        if (!rst_n) begin
            r_a <= 0;
            r_b <= 0;
            r_sum0 <= 0;
            r_sum1 <= 0;
            r_sum2 <= 0;
            r_carry0 <= 0;
            r_carry1 <= 0;
            o_en <= 0;
        end else begin
            if (i_en) begin
                r_a <= adda;
                r_b <= addb;
            end
            r_sum0 <= r_a + r_b;
            r_carry0 <= r_sum0[63];
            r_sum1 <= r_sum0[62:0] + r_carry0;
            r_carry1 <= r_sum1[63];
            r_sum2 <= r_sum1[62:0] + r_carry1;
            o_en <= 1;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
4 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_200103_669320_45d5dc__sample_2
generated.v preview 
module adder_pipe_64bit(
    input clk, rst_n, i_en,
    input [63:0] adda, addb,
    output reg [64:0] result,
    output reg o_en
);

    reg [63:0] reg_a, reg_b;
    reg [63:0] reg_sum;
    reg [63:0] reg_carry;

    always @(posedge clk) begin
        if (!rst_n) begin
            reg_a <= 0;
            reg_b <= 0;
            reg_sum <= 0;
            reg_carry <= 0;
            o_en <= 0;
        end else begin
            if (i_en) begin
                reg_a <= adda;
                reg_b <= addb;
            end
            reg_sum <= reg_a + reg_b + reg_carry;
            reg_carry <= reg_sum[63];
            o_en <= reg_sum[64];
        end
    end

    assign result = {reg_carry, reg_sum[63:0]};

endmodule
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
4 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_200103_669320_45d5dc__sample_3
generated.v preview 
module adder_pipe_64bit(
    input clk, rst_n, i_en,
    input [63:0] adda, addb,
    output reg [64:0] result,
    output reg o_en
);

    reg [63:0] reg_a, reg_b;
    reg [63:0] reg_sum1, reg_sum2;
    reg [63:0] reg_carry1, reg_carry2;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            reg_a <= 0;
            reg_b <= 0;
            reg_sum1 <= 0;
            reg_sum2 <= 0;
            reg_carry1 <= 0;
            reg_carry2 <= 0;
            o_en <= 0;
        end else begin
            if (i_en) begin
                reg_a <= adda;
                reg_b <= addb;
            end
            reg_sum1 <= reg_a + reg_b + reg_carry1;
            reg_carry1 <= reg_sum1[63];
            reg_sum2 <= reg_sum1[62:0] + reg_carry2;
            reg_carry2 <= reg_sum2[63];
            result <= {reg_carry2, reg_sum2};
            o_en <= 1;
        end
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
4 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_200103_669320_45d5dc__sample_4
generated.v preview 
module adder_pipe_64bit(
    input clk, rst_n, i_en,
    input [63:0] adda, addb,
    output reg [64:0] result,
    output reg o_en
);

    reg [63:0] reg_a, reg_b;
    reg [63:0] sum0, sum1, sum2;
    reg [1:0] carry;

    always @(posedge clk) begin
        if (!rst_n) begin
            reg_a <= 0;
            reg_b <= 0;
            sum0 <= 0;
            sum1 <= 0;
            sum2 <= 0;
            carry <= 0;
            o_en <= 0;
        end else begin
            if (i_en) begin
                reg_a <= adda;
                reg_b <= addb;
            end
            sum0 <= reg_a + reg_b;
            carry <= sum0[63];
            sum1 <= sum0[62:0] + carry;
            carry <= sum1[63];
            sum2 <= sum1[62:0] + carry;
            o_en <= (sum2[63] == 1'b1);
            result <= {sum2[62:0], o_en};
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
4 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_200103_669320_45d5dc__sample_5
generated.v preview 
module adder_pipe_64bit(
    input clk, rst_n, i_en,
    input [63:0] adda, addb,
    output reg [64:0] result,
    output reg o_en
);

    reg [63:0] reg_a, reg_b;
    reg [63:0] reg_sum;
    reg [63:0] reg_carry;

    always @(posedge clk) begin
        if (!rst_n) begin
            reg_a <= 0;
            reg_b <= 0;
            reg_sum <= 0;
            reg_carry <= 0;
            o_en <= 0;
        end else begin
            if (i_en) begin
                reg_a <= adda;
                reg_b <= addb;
            end
            reg_sum <= reg_a + reg_b + reg_carry;
            reg_carry <= reg_sum[63];
            o_en <= reg_sum[64];
            result <= reg_sum;
        end
    end

endmodule
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
4 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_200103_669320_45d5dc__sample_6
generated.v preview 
module adder_pipe_64bit(
    input clk, rst_n, i_en,
    input [63:0] adda, addb,
    output reg [64:0] result,
    output reg o_en
);

    reg [63:0] reg_a, reg_b;
    reg [63:0] reg_sum0, reg_sum1;
    reg [63:0] reg_carry0, reg_carry1;

    always @(posedge clk) begin
        if (!rst_n) begin
            reg_a <= 0;
            reg_b <= 0;
            reg_sum0 <= 0;
            reg_sum1 <= 0;
            reg_carry0 <= 0;
            reg_carry1 <= 0;
            o_en <= 0;
        end else begin
            if (i_en) begin
                reg_a <= adda;
                reg_b <= addb;
            end
            reg_sum0 <= reg_a + reg_b + reg_carry0;
            reg_carry0 <= reg_sum0[63];
            reg_sum1 <= reg_sum0[62:0] + reg_carry0;
            reg_carry1 <= reg_sum1[63];
            result <= {reg_carry1, reg_sum1};
            o_en <= 1;
        end
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
4 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_200103_669320_45d5dc__sample_7
generated.v preview 
module adder_pipe_64bit(
    input clk, rst_n, i_en,
    input [63:0] adda, addb,
    output reg [64:0] result,
    output reg o_en
);

    reg [63:0] reg_a, reg_b;
    reg [63:0] reg_sum;
    reg [63:0] reg_carry;

    always @(posedge clk) begin
        if (!rst_n) begin
            reg_a <= 0;
            reg_b <= 0;
            reg_sum <= 0;
            reg_carry <= 0;
            o_en <= 0;
        end else begin
            if (i_en) begin
                reg_a <= adda;
                reg_b <= addb;
            end
            reg_sum <= reg_a + reg_b + reg_carry;
            reg_carry <= reg_sum[63];
            o_en <= reg_sum[64];
            result <= reg_sum;
        end
    end

endmodule
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
4 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_200103_669320_45d5dc__sample_8
generated.v preview 
module adder_pipe_64bit(
    input clk, rst_n, i_en,
    input [63:0] adda, addb,
    output reg [64:0] result,
    output reg o_en
);

    reg [63:0] reg_a, reg_b;
    reg [63:0] reg_sum1, reg_sum2;
    reg [63:0] reg_carry1, reg_carry2;

    always @(posedge clk) begin
        if (!rst_n) begin
            reg_a <= 0;
            reg_b <= 0;
            reg_sum1 <= 0;
            reg_sum2 <= 0;
            reg_carry1 <= 0;
            reg_carry2 <= 0;
            o_en <= 0;
        end else begin
            if (i_en) begin
                reg_a <= adda;
                reg_b <= addb;
            end
            reg_sum1 <= reg_a + reg_b + reg_carry1;
            reg_carry1 <= reg_sum1[63];
            reg_sum2 <= reg_sum1[62:0] + reg_carry2;
            reg_carry2 <= reg_sum2[63];
            result <= reg_sum2;
            o_en <= 1;
        end
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
4 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_200103_669320_45d5dc__sample_9
generated.v preview 
module adder_pipe_64bit(
    input clk, rst_n, i_en,
    input [63:0] adda, addb,
    output reg [64:0] result,
    output reg o_en
);

    reg [63:0] r_a, r_b;
    reg [63:0] r_sum0, r_sum1;
    reg [63:0] r_carry0, r_carry1;

    always @(posedge clk) begin
        if (!rst_n) begin
            r_a <= 0;
            r_b <= 0;
            r_sum0 <= 0;
            r_sum1 <= 0;
            r_carry0 <= 0;
            r_carry1 <= 0;
            o_en <= 0;
        end else begin
            if (i_en) begin
                r_a <= adda;
                r_b <= addb;
            end
            r_sum0 <= r_a + r_b + r_carry0;
            r_carry0 <= r_sum0[63];
            r_sum1 <= r_sum0[62:0] + r_carry0;
            r_carry1 <= r_sum1[63];
            result <= {r_carry1, r_sum1};
            o_en <= 1;
        end
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
4 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_200103_669320_45d5dc__sample_10
generated.v preview 
module adder_pipe_64bit(
    input clk, rst_n, i_en,
    input [63:0] adda, addb,
    output reg [64:0] result,
    output reg o_en
);

    reg [63:0] reg_a, reg_b;
    reg [63:0] reg_sum0, reg_sum1, reg_sum2;
    reg [63:0] reg_carry0, reg_carry1;

    always @(posedge clk) begin
        if (!rst_n) begin
            reg_a <= 0;
            reg_b <= 0;
            reg_sum0 <= 0;
            reg_sum1 <= 0;
            reg_sum2 <= 0;
            reg_carry0 <= 0;
            reg_carry1 <= 0;
            o_en <= 0;
        end else begin
            if (i_en) begin
                reg_a <= adda;
                reg_b <= addb;
            end
            reg_sum0 <= reg_a + reg_b;
            reg_carry0 <= reg_sum0[63];
            reg_sum1 <= reg_sum0[62:0] + reg_carry0;
            reg_carry1 <= reg_sum1[63];
            reg_sum2 <= reg_sum1[62:0] + reg_carry1;
            o_en <= reg_sum2[63];
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
4 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}