codegemma:7b | RAG off

13_rtllm_arithmetic / task_07 | comparator_3bit

benchmarkrtllm

task_idrtllm/13_rtllm_arithmetic/task_07

samples_total10

final_success_samples10

final_success_rate_samples100.0%

functional_pass_rate_samples100.0%

synth_pass_rate_samples100.0%

source_runsrun_20260427_200103_669320_45d5dc

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample	run	extract_ok	syntax_ok	functional_ok	openlane_ok	final_success	failure_stage	failure_reason	details
sample_1	run_20260427_200103_669320_45d5dc	ok	ok	ok	ok	ok	success	Full pipeline success	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_07\samples\run_20260427_200103_669320_45d5dc__sample_1 generated.v preview module comparator_3bit( input logic [2:0] A, input logic [2:0] B, output logic A_greater, output logic A_equal, output logic A_less ); assign A_greater = A > B; assign A_equal = A == B; assign A_less = A < B; endmodule functional details [stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_07/tb.v:48: $finish called at 1000000 (1ps) synthesis details [error] None outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": true, "syntax_required": true, "functional_required": true, "openlane_required": true, "final_success": true, "success": true }
sample_2	run_20260427_200103_669320_45d5dc	ok	ok	ok	ok	ok	success	Full pipeline success	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_07\samples\run_20260427_200103_669320_45d5dc__sample_2 generated.v preview module comparator_3bit( input wire [2:0] A, input wire [2:0] B, output wire A_greater, output wire A_equal, output wire A_less ); assign A_greater = (A > B); assign A_equal = (A == B); assign A_less = (A < B); endmodule functional details [stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_07/tb.v:48: $finish called at 1000000 (1ps) synthesis details [error] None outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": true, "syntax_required": true, "functional_required": true, "openlane_required": true, "final_success": true, "success": true }
sample_3	run_20260427_200103_669320_45d5dc	ok	ok	ok	ok	ok	success	Full pipeline success	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_07\samples\run_20260427_200103_669320_45d5dc__sample_3 generated.v preview module comparator_3bit( input logic [2:0] A, input logic [2:0] B, output logic A_greater, output logic A_equal, output logic A_less ); assign A_greater = A > B; assign A_equal = A == B; assign A_less = A < B; endmodule functional details [stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_07/tb.v:48: $finish called at 1000000 (1ps) synthesis details [error] None outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": true, "syntax_required": true, "functional_required": true, "openlane_required": true, "final_success": true, "success": true }
sample_4	run_20260427_200103_669320_45d5dc	ok	ok	ok	ok	ok	success	Full pipeline success	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_07\samples\run_20260427_200103_669320_45d5dc__sample_4 generated.v preview module comparator_3bit( input logic [2:0] A, input logic [2:0] B, output logic A_greater, output logic A_equal, output logic A_less ); assign A_greater = A > B; assign A_equal = A == B; assign A_less = A < B; endmodule functional details [stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_07/tb.v:48: $finish called at 1000000 (1ps) synthesis details [error] None outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": true, "syntax_required": true, "functional_required": true, "openlane_required": true, "final_success": true, "success": true }
sample_5	run_20260427_200103_669320_45d5dc	ok	ok	ok	ok	ok	success	Full pipeline success	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_07\samples\run_20260427_200103_669320_45d5dc__sample_5 generated.v preview module comparator_3bit( input logic [2:0] A, input logic [2:0] B, output logic A_greater, output logic A_equal, output logic A_less ); assign A_greater = A > B; assign A_equal = A == B; assign A_less = A < B; endmodule functional details [stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_07/tb.v:48: $finish called at 1000000 (1ps) synthesis details [error] None outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": true, "syntax_required": true, "functional_required": true, "openlane_required": true, "final_success": true, "success": true }
sample_6	run_20260427_200103_669320_45d5dc	ok	ok	ok	ok	ok	success	Full pipeline success	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_07\samples\run_20260427_200103_669320_45d5dc__sample_6 generated.v preview module comparator_3bit( input logic [2:0] A, input logic [2:0] B, output logic A_greater, output logic A_equal, output logic A_less ); assign A_greater = A > B; assign A_equal = A == B; assign A_less = A < B; endmodule functional details [stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_07/tb.v:48: $finish called at 1000000 (1ps) synthesis details [error] None outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": true, "syntax_required": true, "functional_required": true, "openlane_required": true, "final_success": true, "success": true }
sample_7	run_20260427_200103_669320_45d5dc	ok	ok	ok	ok	ok	success	Full pipeline success	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_07\samples\run_20260427_200103_669320_45d5dc__sample_7 generated.v preview module comparator_3bit( input logic [2:0] A, input logic [2:0] B, output logic A_greater, output logic A_equal, output logic A_less ); assign A_greater = A > B; assign A_equal = A == B; assign A_less = A < B; endmodule functional details [stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_07/tb.v:48: $finish called at 1000000 (1ps) synthesis details [error] None outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": true, "syntax_required": true, "functional_required": true, "openlane_required": true, "final_success": true, "success": true }
sample_8	run_20260427_200103_669320_45d5dc	ok	ok	ok	ok	ok	success	Full pipeline success	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_07\samples\run_20260427_200103_669320_45d5dc__sample_8 generated.v preview module comparator_3bit( input logic [2:0] A, input logic [2:0] B, output logic A_greater, output logic A_equal, output logic A_less ); assign A_greater = A > B; assign A_equal = A == B; assign A_less = A < B; endmodule functional details [stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_07/tb.v:48: $finish called at 1000000 (1ps) synthesis details [error] None outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": true, "syntax_required": true, "functional_required": true, "openlane_required": true, "final_success": true, "success": true }
sample_9	run_20260427_200103_669320_45d5dc	ok	ok	ok	ok	ok	success	Full pipeline success	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_07\samples\run_20260427_200103_669320_45d5dc__sample_9 generated.v preview module comparator_3bit( input logic [2:0] A, input logic [2:0] B, output logic A_greater, output logic A_equal, output logic A_less ); assign A_greater = A > B; assign A_equal = A == B; assign A_less = A < B; endmodule functional details [stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_07/tb.v:48: $finish called at 1000000 (1ps) synthesis details [error] None outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": true, "syntax_required": true, "functional_required": true, "openlane_required": true, "final_success": true, "success": true }
sample_10	run_20260427_200103_669320_45d5dc	ok	ok	ok	ok	ok	success	Full pipeline success	Open details sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_07\samples\run_20260427_200103_669320_45d5dc__sample_10 generated.v preview module comparator_3bit( input logic [2:0] A, input logic [2:0] B, output logic A_greater, output logic A_equal, output logic A_less ); assign A_greater = A > B; assign A_equal = A == B; assign A_less = A < B; endmodule functional details [stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_07/tb.v:48: $finish called at 1000000 (1ps) synthesis details [error] None outcome { "llm_ok": true, "extract_ok": true, "syntax_ok": true, "functional_ok": true, "openlane_ok": true, "syntax_required": true, "functional_required": true, "openlane_required": true, "final_success": true, "success": true }