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13_rtllm_arithmetic / task_10 | verified_radix2_div

benchmarkrtllm
task_idrtllm/13_rtllm_arithmetic/task_10
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260427_200103_669320_45d5dc

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_200103_669320_45d5dc__sample_1
generated.v preview 
module radix2_div(
    input clk, rst, sign, opn_valid, res_ready,
    input [7:0] dividend, divisor,
    output reg res_valid,
    output reg [15:0] result
);

    reg [7:0] SR;
    reg [7:0] NEG_DIVISOR;
    reg [2:0] cnt, start_cnt;

    always @(posedge clk) begin
        if (rst) begin
            SR <= 8'b0;
            NEG_DIVISOR <= 8'b0;
            cnt <= 0;
            start_cnt <= 0;
            res_valid <= 0;
        end else begin
            if (opn_valid && !res_valid) begin
                SR <= {sign ? {8'b1, dividend} : dividend};
                NEG_DIVISOR <= {sign ? {8'b1, divisor} : divisor};
                cnt <= 1;
                start_cnt <= 1;
            end

            if (start_cnt) begin
                if (cnt == 8) begin
                    cnt <= 0;
                    start_cnt <= 0;
                    result <= {SR, {8'b0}};
                    res_valid <= 1;
...
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_error",
    "message": "error",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_200103_669320_45d5dc__sample_2
generated.v preview 
module radix2_div(
    input clk, rst, sign, opn_valid, res_ready,
    input [7:0] dividend, divisor,
    output reg res_valid,
    output reg [15:0] result
);

    reg [7:0] SR;
    reg [7:0] NEG_DIVISOR;
    reg [2:0] cnt, start_cnt;

    always @(posedge clk) begin
        if (rst) begin
            SR <= 8'b0;
            NEG_DIVISOR <= 8'b0;
            cnt <= 0;
            start_cnt <= 0;
            res_valid <= 0;
        end else begin
            if (opn_valid && !res_valid) begin
                SR <= {sign ? {8'b1, dividend} : dividend};
                NEG_DIVISOR <= {sign ? {8'b1, divisor} : divisor};
                cnt <= 1;
                start_cnt <= 1;
            end

            if (start_cnt) begin
                if (cnt == 8) begin
                    cnt <= 0;
                    start_cnt <= 0;
                    result <= {SR, {8'd0}};
                    res_valid <= 1;
...
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_error",
    "message": "error",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_200103_669320_45d5dc__sample_3
generated.v preview 
module radix2_div(
    input clk, rst, sign, opn_valid, res_ready,
    input [7:0] dividend, divisor,
    output reg res_valid,
    output reg [15:0] result
);

    reg [7:0] SR;
    reg [7:0] NEG_DIVISOR;
    reg [2:0] cnt, start_cnt;

    always @(posedge clk) begin
        if (rst) begin
            SR <= 8'b0;
            NEG_DIVISOR <= 8'b0;
            cnt <= 0;
            start_cnt <= 0;
            res_valid <= 0;
        end else begin
            if (opn_valid && !res_valid) begin
                SR <= {sign ? {8'b1, dividend} : dividend};
                NEG_DIVISOR <= {sign ? {8'b1, divisor} : divisor};
                cnt <= 1;
                start_cnt <= 1;
            end

            if (start_cnt) begin
                if (cnt == 8'b1000) begin
                    cnt <= 0;
                    start_cnt <= 0;
                    result <= {SR, {8'd0}};
                    res_valid <= 1;
...
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_error",
    "message": "error",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_200103_669320_45d5dc__sample_4
generated.v preview 
module radix2_div(
    input clk, rst, sign, opn_valid, res_ready,
    input [7:0] dividend, divisor,
    output reg res_valid,
    output reg [15:0] result
);

    reg [7:0] SR;
    reg [7:0] NEG_DIVISOR;
    reg [2:0] cnt, start_cnt;

    always @(posedge clk) begin
        if (rst) begin
            SR <= 8'b0;
            NEG_DIVISOR <= 8'b0;
            cnt <= 0;
            start_cnt <= 0;
            res_valid <= 0;
        end else begin
            if (opn_valid && !res_valid) begin
                SR <= {sign ? {8'b1, dividend} : dividend};
                NEG_DIVISOR <= {sign ? {8'b1, divisor} : -divisor};
                cnt <= 1;
                start_cnt <= 1;
            end else if (start_cnt) begin
                if (cnt == 8) begin
                    cnt <= 0;
                    start_cnt <= 0;
                    result <= {SR, {8'b0}};
                    res_valid <= 1;
                end else begin
                    cnt <= cnt + 1;
...
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_error",
    "message": "error",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_5/generated.v:21: error: No function named `abs' found in this context (verified_radix2_div.uut).
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_200103_669320_45d5dc__sample_5
generated.v preview 
module radix2_div(
    input clk, rst, sign, opn_valid, res_ready,
    input [7:0] dividend, divisor,
    output reg res_valid,
    output reg [15:0] result
);

    reg [7:0] SR;
    reg [7:0] NEG_DIVISOR;
    reg [2:0] cnt, start_cnt;

    always @(posedge clk) begin
        if (rst) begin
            SR <= 8'b0;
            NEG_DIVISOR <= 8'b0;
            cnt <= 0;
            start_cnt <= 0;
            res_valid <= 0;
        end else begin
            if (opn_valid && !res_valid) begin
                SR <= abs(dividend) << 1;
                NEG_DIVISOR <= -abs(divisor);
                cnt <= 1;
                start_cnt <= 1;
            end

            if (start_cnt == 8'b111) begin
                cnt <= 0;
                start_cnt <= 0;
                result <= {SR, {8'b0}};
                res_valid <= 1;
            end else begin
...
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_5/generated.v:21: error: No function named `abs' found in this context (verified_radix2_div.uut).
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_5/generated.v:22: error: No function named `abs' found in this context (verified_radix2_div.uut).
2 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_5/functional/generated.v:21: error: No function named `abs' found in this context (radix2_div_tb.uut).
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_5/functional/generated.v:22: error: No function named `abs' found in this context (radix2_div_tb.uut).
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_5/functional/generated.v:21: error: No function named `abs' found in this context (verified_radix2_div.uut).
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_5/functional/generated.v:22: error: No function named `abs' found in this context (verified_radix2_div.uut).
4 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_5/generated.v:21: error: No function named `abs' found in this context (verified_radix2_div.uut).\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_5/generated.v:22: error: No function named `abs' found in this context (verified_radix2_div.uut).\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_5/functional/generated.v:21: error: No function named `abs' found in this context (radix2_div_tb.uut).\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_5/functional/generated.v:22: error: No function named `abs' found in this context (radix2_div_tb.uut).\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_5/functional/generated.v:21: error: No function named `abs' found in this context (verified_radix2_div.uut).\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_5/functional/generated.v:22: error: No function named `abs' found in this context (verified_radix2_div.uut).\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_200103_669320_45d5dc__sample_6
generated.v preview 
module radix2_div(
    input clk, rst, sign, opn_valid, res_ready,
    input [7:0] dividend, divisor,
    output reg res_valid,
    output reg [15:0] result
);

    reg [7:0] SR;
    reg [7:0] NEG_DIVISOR;
    reg [2:0] cnt, start_cnt;

    always @(posedge clk) begin
        if (rst) begin
            SR <= 8'b0;
            NEG_DIVISOR <= 8'b0;
            cnt <= 0;
            start_cnt <= 0;
            res_valid <= 0;
        end else begin
            if (opn_valid && !res_valid) begin
                SR <= {sign ? {8'b1, dividend} : dividend};
                NEG_DIVISOR <= {sign ? {8'b1, divisor} : -divisor};
                cnt <= 1;
                start_cnt <= 1;
            end else if (start_cnt) begin
                if (cnt == 8) begin
                    cnt <= 0;
                    start_cnt <= 0;
                    result <= {SR, {8'd0}};
                    res_valid <= 1;
                end else begin
                    cnt <= cnt + 1;
...
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_error",
    "message": "error",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/generated.v:34: error: Concatenation operand "((SR['sd7])^(NEG_DIVISOR['sd7]))&('sd1)" has indefinite width.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_200103_669320_45d5dc__sample_7
generated.v preview 
module radix2_div(
    input clk, rst, sign, opn_valid, res_ready,
    input [7:0] dividend, divisor,
    output reg res_valid,
    output reg [15:0] result
);

    reg [7:0] SR;
    reg [7:0] NEG_DIVISOR;
    reg [2:0] cnt, start_cnt;

    always @(posedge clk) begin
        if (rst) begin
            SR <= 8'b0;
            NEG_DIVISOR <= 8'b0;
            cnt <= 0;
            start_cnt <= 0;
            res_valid <= 0;
        end else begin
            if (opn_valid && !res_valid) begin
                SR <= {sign ? {8'b1, dividend} : dividend};
                NEG_DIVISOR <= {sign ? {8'b1, divisor} : -divisor};
                cnt <= 1;
                start_cnt <= 1;
            end else if (start_cnt) begin
                if (cnt == 8) begin
                    cnt <= 0;
                    start_cnt <= 0;
                    result <= {SR, {8'd0}};
                    res_valid <= 1;
                end else begin
                    cnt <= cnt + 1;
...
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/generated.v:34: error: Concatenation operand "((SR['sd7])^(NEG_DIVISOR['sd7]))&('sd1)" has indefinite width.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/generated.v:49: warning: Port 9 (result) of radix2_div expects 16 bits, got 1.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/generated.v:49:        : Padding 15 high bits of the port.
1 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/functional/generated.v:34: error: Concatenation operand "((SR['sd7])^(NEG_DIVISOR['sd7]))&('sd1)" has indefinite width.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/functional/generated.v:34: error: Concatenation operand "((SR['sd7])^(NEG_DIVISOR['sd7]))&('sd1)" has indefinite width.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/functional/generated.v:49: warning: Port 9 (result) of radix2_div expects 16 bits, got 1.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/functional/generated.v:49:        : Padding 15 high bits of the port.
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/generated.v:34: error: Concatenation operand \"((SR['sd7])^(NEG_DIVISOR['sd7]))&('sd1)\" has indefinite width.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/generated.v:49: warning: Port 9 (result) of radix2_div expects 16 bits, got 1.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/generated.v:49:        : Padding 15 high bits of the port.\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/functional/generated.v:34: error: Concatenation operand \"((SR['sd7])^(NEG_DIVISOR['sd7]))&('sd1)\" has indefinite width.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/functional/generated.v:34: error: Concatenation operand \"((SR['sd7])^(NEG_DIVISOR['sd7]))&('sd1)\" has indefinite width.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/functional/generated.v:49: warning: Port 9 (result) of radix2_div expects 16 bits, got 1.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_7/functional/generated.v:49:        : Padding 15 high bits of the port.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_200103_669320_45d5dc__sample_8
generated.v preview 
module radix2_div(
    input clk, rst, sign, opn_valid, res_ready,
    input [7:0] dividend, divisor,
    output reg res_valid,
    output reg [15:0] result
);

    reg [7:0] SR;
    reg [7:0] NEG_DIVISOR;
    reg [2:0] cnt, start_cnt;

    always @(posedge clk) begin
        if (rst) begin
            SR <= 8'b0;
            NEG_DIVISOR <= 8'b0;
            cnt <= 0;
            start_cnt <= 0;
            res_valid <= 0;
        end else begin
            if (opn_valid && !res_valid) begin
                SR <= dividend;
                NEG_DIVISOR <= ~divisor;
                cnt <= 1;
                start_cnt <= 1;
            end

            if (start_cnt == 8'b100) begin
                res_valid <= 1;
                result <= {SR, cnt};
                start_cnt <= 0;
            end else begin
                cnt <= cnt + 1;
...
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_8/generated.v:47: warning: Port 4 (opn_valid) of radix2_div expects 1 bits, got 8.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_8/generated.v:47:        : Pruning 7 high bits of the expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_8/generated.v:47: warning: Port 5 (res_ready) of radix2_div expects 1 bits, got 8.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_8/generated.v:47:        : Pruning 7 high bits of the expression.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_8/generated.v:47: warning: Port 6 (dividend) of radix2_div expects 8 bits, got 1.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_8/generated.v:47:        : Padding 7 high bits of the port.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_8/generated.v:47: warning: Port 7 (divisor) of radix2_div expects 8 bits, got 1.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_10/sample_8/generated.v:47:        : Padding 7 high bits of the port.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_error",
    "message": "error",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_200103_669320_45d5dc__sample_9
generated.v preview 
module radix2_div(
    input clk, rst, sign, opn_valid, res_ready,
    input [7:0] dividend, divisor,
    output reg res_valid,
    output reg [15:0] result
);

    reg [7:0] SR;
    reg [7:0] NEG_DIVISOR;
    reg [2:0] cnt, start_cnt;

    always @(posedge clk) begin
        if (rst) begin
            SR <= 8'b0;
            NEG_DIVISOR <= 8'b0;
            cnt <= 0;
            start_cnt <= 0;
            res_valid <= 0;
        end else begin
            if (opn_valid && !res_valid) begin
                SR <= dividend;
                NEG_DIVISOR <= ~divisor;
                cnt <= 1;
                start_cnt <= 1;
            end

            if (start_cnt) begin
                if (cnt == 8'b1000) begin
                    cnt <= 0;
                    start_cnt <= 0;
                    result <= {SR, {8'b0}};
                    res_valid <= 1;
...
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_error",
    "message": "error",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260427_200103_669320_45d5dc ok ok failed skipped failed functional error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_200103_669320_45d5dc__sample_10
generated.v preview 
module radix2_div(
    input clk, rst, sign, opn_valid, res_ready,
    input [7:0] dividend, divisor,
    output reg res_valid,
    output reg [15:0] result
);

    reg [7:0] SR;
    reg [7:0] NEG_DIVISOR;
    reg [2:0] cnt, start_cnt;

    always @(posedge clk) begin
        if (rst) begin
            SR <= 8'b0;
            NEG_DIVISOR <= 8'b0;
            cnt <= 0;
            start_cnt <= 0;
            res_valid <= 0;
        end else begin
            if (opn_valid && !res_valid) begin
                SR <= dividend;
                NEG_DIVISOR <= ~divisor;
                cnt <= 1;
                start_cnt <= 1;
            end

            if (start_cnt) begin
                if (cnt == 8'b1000) begin
                    cnt <= 0;
                    start_cnt <= 0;
                    result <= {SR, {8'b0}};
                    res_valid <= 1;
...
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_error",
    "message": "error",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}