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codegemma:7b | RAG off

13_rtllm_arithmetic / task_16 | fixed_point_adder

benchmarkrtllm
task_idrtllm/13_rtllm_arithmetic/task_16
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260427_200103_669320_45d5dc

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_1/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_16\samples\run_20260427_200103_669320_45d5dc__sample_1
generated.v preview 
module fixed_point_adder(
    input logic [N-1:0] a,
    input logic [N-1:0] b,
    output logic [N-1:0] c
);

    parameter Q = 8; // Number of fractional bits
    parameter N = 16; // Total number of bits

    reg [N-1:0] res;

    always @(posedge clk) begin
        if (a[N-1] == b[N-1]) begin
            res = a + b;
        end else begin
            if (a[N-1] == 1'b0) begin
                res = a - b;
            end else begin
                res = b - a;
            end
        end
    end

    assign c = res;

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_1/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_1/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
2 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_1/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_1/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_1/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_1/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_1/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_1/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_2/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_16\samples\run_20260427_200103_669320_45d5dc__sample_2
generated.v preview 
module fixed_point_adder(
    input wire [N-1:0] a,
    input wire [N-1:0] b,
    output wire [N-1:0] c
);

    parameter Q = 8; // Number of fractional bits
    parameter N = 16; // Total number of bits

    reg [N-1:0] res;

    always @(posedge clk) begin
        if (a[N-1] == b[N-1]) begin
            res = a + b;
        end else begin
            if (a[N-1] == 1'b0) begin
                res = a - b;
            end else begin
                res = b - a;
            end
        end
    end

    assign c = res;

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_2/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_2/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
2 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_2/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_2/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_2/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_2/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_2/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_2/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_3/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_16\samples\run_20260427_200103_669320_45d5dc__sample_3
generated.v preview 
module fixed_point_adder(
    input logic [N-1:0] a,
    input logic [N-1:0] b,
    output logic [N-1:0] c
);

    parameter Q = 8; // Number of fractional bits
    parameter N = 16; // Total number of bits

    reg [N-1:0] res;

    always @(posedge clk) begin
        if (a[N-1] == b[N-1]) begin // Absolute value addition
            res = a + b;
        end else begin // Absolute value subtraction
            if (a[N-1] == 1'b0) begin
                res = a - b;
            end else begin
                res = b - a;
            end
        end

        c = res;
    end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_3/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_3/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
2 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_3/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_3/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_3/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_3/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_3/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_3/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_4/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_16\samples\run_20260427_200103_669320_45d5dc__sample_4
generated.v preview 
module fixed_point_adder(
    input  wire [N-1:0] a,
    input  wire [N-1:0] b,
    output wire [N-1:0] c
);

    parameter Q = 8; // Fractional bits
    parameter N = 16; // Total bits

    reg [N-1:0] res;

    always @(posedge clk) begin
        if (a[N-1] == b[N-1]) begin
            res = a + b;
        end else begin
            if (a[N-1] == 1'b0) begin
                res = a - b;
            end else begin
                res = b - a;
            end
        end
    end

    assign c = res;

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_4/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_4/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
2 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_4/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_4/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_4/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_4/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_4/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_4/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/generated.v:23: error: c is not a valid l-value in fixed_point_adder.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_16\samples\run_20260427_200103_669320_45d5dc__sample_5
generated.v preview 
module fixed_point_adder(
    input  wire [N-1:0] a,
    input  wire [N-1:0] b,
    output wire [N-1:0] c
);

    parameter Q = 8; // Fractional bits
    parameter N = 16; // Total bits

    reg [N-1:0] res;

    always @(posedge clk) begin
        if (a[N-1] == b[N-1]) begin // Absolute Value Addition
            res = a + b;
        end else begin // Absolute Value Subtraction
            if (a[N-1] == 1'b0) begin
                res = a - b;
            end else begin
                res = b - a;
            end
        end

        c <= res;
    end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/generated.v:23: error: c is not a valid l-value in fixed_point_adder.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/generated.v:4:      : c is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
3 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/functional/generated.v:23: error: c is not a valid l-value in testbench.fp_adder.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/functional/generated.v:4:      : c is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/generated.v:23: error: c is not a valid l-value in fixed_point_adder.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/generated.v:4:      : c is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/functional/generated.v:23: error: c is not a valid l-value in testbench.fp_adder.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/functional/generated.v:4:      : c is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_5/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/generated.v:23: error: c is not a valid l-value in fixed_point_adder.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_16\samples\run_20260427_200103_669320_45d5dc__sample_6
generated.v preview 
module fixed_point_adder(
    input  wire [N-1:0] a,
    input  wire [N-1:0] b,
    output wire [N-1:0] c
);

    parameter Q = 8; // Fractional bits
    parameter N = 16; // Total bits

    reg [N-1:0] res;

    always @(posedge clk) begin
        if (a[N-1] == b[N-1]) begin // Absolute Value Addition
            res = a + b;
        end else begin // Absolute Value Subtraction
            if (a[N-1] == 1'b0) begin
                res = a - b;
            end else begin
                res = b - a;
            end
        end

        c <= res;
    end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/generated.v:23: error: c is not a valid l-value in fixed_point_adder.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/generated.v:4:      : c is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
3 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/functional/generated.v:23: error: c is not a valid l-value in testbench.fp_adder.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/functional/generated.v:4:      : c is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/generated.v:23: error: c is not a valid l-value in fixed_point_adder.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/generated.v:4:      : c is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/functional/generated.v:23: error: c is not a valid l-value in testbench.fp_adder.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/functional/generated.v:4:      : c is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_6/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/generated.v:23: error: c is not a valid l-value in fixed_point_adder.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_16\samples\run_20260427_200103_669320_45d5dc__sample_7
generated.v preview 
module fixed_point_adder(
    input  wire [N-1:0] a,
    input  wire [N-1:0] b,
    output wire [N-1:0] c
);

    parameter Q = 8; // Fractional bits
    parameter N = 16; // Total bits

    reg [N-1:0] res;

    always @(posedge clk) begin
        if (a[N-1] == b[N-1]) begin // Absolute value addition
            res = a + b;
        end else begin // Absolute value subtraction
            if (a[N-1] == 1'b0) begin
                res = a - b;
            end else begin
                res = b - a;
            end
        end

        c <= res;
    end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/generated.v:23: error: c is not a valid l-value in fixed_point_adder.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/generated.v:4:      : c is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
3 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/functional/generated.v:23: error: c is not a valid l-value in testbench.fp_adder.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/functional/generated.v:4:      : c is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/generated.v:23: error: c is not a valid l-value in fixed_point_adder.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/generated.v:4:      : c is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/functional/generated.v:23: error: c is not a valid l-value in testbench.fp_adder.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/functional/generated.v:4:      : c is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_7/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/generated.v:23: error: c is not a valid l-value in fixed_point_adder.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_16\samples\run_20260427_200103_669320_45d5dc__sample_8
generated.v preview 
module fixed_point_adder(
    input  wire [N-1:0] a,
    input  wire [N-1:0] b,
    output wire [N-1:0] c
);

    parameter Q = 8; // Fractional bits
    parameter N = 16; // Total bits

    reg [N-1:0] res;

    always @(posedge clk) begin
        if (a[N-1] == b[N-1]) begin // Absolute value addition
            res = a + b;
        end else begin // Absolute value subtraction
            if (a[N-1] == 1'b0) begin
                res = a - b;
            end else begin
                res = b - a;
            end
        end

        c <= res;
    end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/generated.v:23: error: c is not a valid l-value in fixed_point_adder.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/generated.v:4:      : c is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
3 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/functional/generated.v:23: error: c is not a valid l-value in testbench.fp_adder.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/functional/generated.v:4:      : c is declared here as wire.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/generated.v:23: error: c is not a valid l-value in fixed_point_adder.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/generated.v:4:      : c is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/functional/generated.v:23: error: c is not a valid l-value in testbench.fp_adder.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/functional/generated.v:4:      : c is declared here as wire.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_8/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax _9/generated.v:3: error: Unable to bind parameter `N' in `fixed_point_adder'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_16\samples\run_20260427_200103_669320_45d5dc__sample_9
generated.v preview 
module fixed_point_adder(
    input  wire [N-1:0] a,
    input  wire [N-1:0] b,
    output wire [N-1:0] c
);

    reg [N-1:0] res;

    always @(posedge clk) begin
        if (a[N-1] == b[N-1]) begin
            res = a + b;
        end else begin
            if (a[N-1] == 1'b0) begin
                res = a - b;
            end else begin
                res = b - a;
            end
        end
    end

    assign c = res;

endmodule
syntax details 
[stderr]
_9/generated.v:3: error: Unable to bind parameter `N' in `fixed_point_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:3: error: Dimensions must be constant.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:3       : This MSB expression violates the rule: (N)-('sd1)
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:4: error: Unable to bind parameter `N' in `fixed_point_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:4: error: Dimensions must be constant.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:4       : This MSB expression violates the rule: (N)-('sd1)
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:7: error: Unable to bind parameter `N' in `fixed_point_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:7: error: Dimensions must be constant.
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:7       : This MSB expression violates the rule: (N)-('sd1)
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:10: error: can not select part of scalar: a
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:10: error: can not select part of scalar: b
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:10: error: Unable to elaborate condition expression.
Elaboration failed
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_16/tb.v:17: error: parameter `N` not found in `testbench.fp_adder`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_16/tb.v:17: error: parameter `Q` not found in `testbench.fp_adder`.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "_9/generated.v:3: error: Unable to bind parameter `N' in `fixed_point_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:3: error: Dimensions must be constant.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:3       : This MSB expression violates the rule: (N)-('sd1)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:4: error: Unable to bind parameter `N' in `fixed_point_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:4: error: Dimensions must be constant.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:4       : This MSB expression violates the rule: (N)-('sd1)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:7: error: Unable to bind parameter `N' in `fixed_point_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:7: error: Dimensions must be constant.\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:7       : This MSB expression violates the rule: (N)-('sd1)\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:10: error: can not select part of scalar: a\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:10: error: can not select part of scalar: b\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_9/generated.v:10: error: Unable to elaborate condition expression.\nElaboration failed\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_16/tb.v:17: error: parameter `N` not found in `testbench.fp_adder`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_16/tb.v:17: error: parameter `Q` not found in `testbench.fp_adder`.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260427_200103_669320_45d5dc ok failed failed skipped failed syntax /data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_10/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_16\samples\run_20260427_200103_669320_45d5dc__sample_10
generated.v preview 
module fixed_point_adder(
    input wire [N-1:0] a,
    input wire [N-1:0] b,
    output wire [N-1:0] c
);

    parameter Q = 8; // Fractional bits
    parameter N = 16; // Total bits

    reg [N-1:0] res;

    always @(posedge clk) begin
        if (a[N-1] == b[N-1]) begin // Absolute value addition
            res = a + b;
        end else begin // Absolute value subtraction
            if (a[N-1] == 1'b0) begin
                res = a - b;
            end else begin
                res = b - a;
            end
        end
    end

    assign c = res;

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_10/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_10/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
2 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_10/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'
/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_10/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_10/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `fixed_point_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_10/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_10/functional/generated.v:12: error: Unable to bind wire/reg/memory `clk' in `testbench.fp_adder'\n/data/eval/out/run_20260427_200103_669320_45d5dc/tmp/codegemma_7/rtllm__13_rtllm_arithmetic__task_16/sample_10/functional/generated.v:12: error: Failed to evaluate event expression 'posedge clk'.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}