13_rtllm_arithmetic / task_19 | sub_64bit
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_19\samples\run_20260427_200103_669320_45d5dc__sample_1
generated.v previewmodule sub_64bit(
input wire [63:0] A,
input wire [63:0] B,
output wire [63:0] result,
output wire overflow
);
assign result = A - B;
assign overflow = (
(A[63] ^ B[63] ^ result[63]) &
((A[63] ^ result[63]) | (B[63] ^ result[63]))
);
endmodule
functional details[stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_19/tb.v:48: $finish called at 1000000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_2 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_19\samples\run_20260427_200103_669320_45d5dc__sample_2
generated.v previewmodule sub_64bit(
input wire [63:0] A,
input wire [63:0] B,
output wire [63:0] result,
output wire overflow
);
assign result = A - B;
assign overflow = (
(A[63] ^ B[63] ^ result[63]) &
((A[63] ^ result[63]) | (B[63] ^ result[63]))
);
endmodule
functional details[stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_19/tb.v:48: $finish called at 1000000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_3 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_19\samples\run_20260427_200103_669320_45d5dc__sample_3
generated.v previewmodule sub_64bit(
input wire [63:0] A,
input wire [63:0] B,
output wire [63:0] result,
output wire overflow
);
assign result = A - B;
assign overflow = (
(A[63] ^ B[63] ^ result[63]) &
((A[63] ^ result[63]) | (B[63] ^ result[63]))
);
endmodule
functional details[stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_19/tb.v:48: $finish called at 1000000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_4 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_19\samples\run_20260427_200103_669320_45d5dc__sample_4
generated.v previewmodule sub_64bit(
input wire [63:0] A,
input wire [63:0] B,
output wire [63:0] result,
output wire overflow
);
assign result = A - B;
assign overflow = (
(A[63] ^ B[63] ^ result[63]) &
((A[63] ^ B[63]) != (result[63] ^ A[63]))
);
endmodule
functional details[stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_19/tb.v:48: $finish called at 1000000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_5 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_19\samples\run_20260427_200103_669320_45d5dc__sample_5
generated.v previewmodule sub_64bit(
input wire [63:0] A,
input wire [63:0] B,
output wire [63:0] result,
output wire overflow
);
assign result = A - B;
assign overflow = (
(A[63] ^ B[63] ^ result[63]) &
((A[63] ^ result[63]) | (B[63] ^ result[63]))
);
endmodule
functional details[stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_19/tb.v:48: $finish called at 1000000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_6 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_19\samples\run_20260427_200103_669320_45d5dc__sample_6
generated.v previewmodule sub_64bit(
input wire [63:0] A,
input wire [63:0] B,
output wire [63:0] result,
output wire overflow
);
assign result = A - B;
assign overflow = (
(A[63] ^ B[63] ^ result[63]) &
((A[63] ^ result[63]) | (B[63] ^ result[63]))
);
endmodule
functional details[stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_19/tb.v:48: $finish called at 1000000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_7 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_19\samples\run_20260427_200103_669320_45d5dc__sample_7
generated.v previewmodule sub_64bit(
input wire [63:0] A,
input wire [63:0] B,
output wire [63:0] result,
output wire overflow
);
assign result = A - B;
assign overflow = (
(A[63] ^ B[63] ^ result[63]) &
((A[63] ^ result[63]) | (B[63] ^ result[63]))
);
endmodule
functional details[stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_19/tb.v:48: $finish called at 1000000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_8 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_19\samples\run_20260427_200103_669320_45d5dc__sample_8
generated.v previewmodule sub_64bit(
input wire [63:0] A,
input wire [63:0] B,
output wire [63:0] result,
output wire overflow
);
assign result = A - B;
wire sign_a = A[63];
wire sign_b = B[63];
wire sign_result = result[63];
assign overflow = (sign_a ^ sign_b) & (~sign_a ^ sign_result);
endmodule
functional details[stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_19/tb.v:48: $finish called at 1000000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_9 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_19\samples\run_20260427_200103_669320_45d5dc__sample_9
generated.v previewmodule sub_64bit(
input wire [63:0] A,
input wire [63:0] B,
output wire [63:0] result,
output wire overflow
);
assign result = A - B;
assign overflow = (
(A[63] ^ B[63] ^ result[63]) &
((A[63] ^ result[63]) | (B[63] ^ result[63]))
);
endmodule
functional details[stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_19/tb.v:48: $finish called at 1000000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_10 | run_20260427_200103_669320_45d5dc | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_19\samples\run_20260427_200103_669320_45d5dc__sample_10
generated.v previewmodule sub_64bit(
input wire [63:0] A,
input wire [63:0] B,
output wire [63:0] result,
output wire overflow
);
assign result = A - B;
wire sign_a = A[63];
wire sign_b = B[63];
wire sign_result = result[63];
assign overflow = (sign_a ^ sign_b) & (~sign_a ^ sign_result);
endmodule
functional details[stdout] =========== Your Design Passed =========== /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_19/tb.v:48: $finish called at 1000000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|