Назад к моделям Назад к профилю модели

codegemma:7b | RAG on

03_low_power_design / task_34 | soc_top

benchmarkilyasov
task_idilyasov/03_low_power_design/task_34
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260425_215014_451219_c08f66

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260425_215014_451219_c08f66 ok ok failed skipped failed functional /workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260425_215014_451219_c08f66__sample_1
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output reg [31:0] data_out
);

    // Instantiate the AON domain controller
    aon_ctrl aon_ctrl_inst(.clk(clk), .sleep_req(sleep_req));

    // Instantiate the DSP domain
    pd_dsp pd_dsp_inst(.clk(clk), .data_in(data_in), .data_out(data_out));

endmodule

module aon_ctrl(
    input clk,
    input sleep_req,
    output reg pwr_enable,
    output reg iso_en
);

    always @(posedge clk) begin
        if (sleep_req) begin
            iso_en <= 1'b1;
            pwr_enable <= 1'b1;
        end else begin
            iso_en <= 1'b0;
            pwr_enable <= 1'b1;
        end
    end
...
functional details 
[stderr]
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.\n/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260425_215014_451219_c08f66 ok ok failed skipped failed functional /workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260425_215014_451219_c08f66__sample_2
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output reg [31:0] data_out
);

    // AON Domain Controller
    aon_ctrl aon(
        .clk(clk),
        .rst_n(rst_n),
        .sleep_req(sleep_req),
        .pwr_enable(aon_pwr_enable),
        .iso_en(aon_iso_en)
    );

    // DSP Domain
    pd_dsp dsp(
        .clk(clk),
        .data_in(data_in),
        .data_out(data_out)
    );

endmodule

module aon_ctrl(
    input clk,
    input rst_n,
    input sleep_req,
    output reg pwr_enable,
    output reg iso_en
...
functional details 
[stderr]
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.\n/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260425_215014_451219_c08f66 ok ok failed skipped failed functional /workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260425_215014_451219_c08f66__sample_3
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output reg [31:0] data_out
);

    // Power domain controllers
    aon_ctrl aon_ctrl(.clk(clk), .sleep_req(sleep_req));
    pd_dsp pd_dsp(.clk(clk), .data_in(data_in), .data_out(data_out));

    // UPF Control Hooks
    assign pwr_enable = aon_ctrl.pwr_enable;
    assign iso_en = aon_ctrl.iso_en;

endmodule

module aon_ctrl(
    input clk,
    input sleep_req,
    output reg pwr_enable,
    output reg iso_en
);

    always @(posedge clk) begin
        if (sleep_req) begin
            iso_en <= 1'b1;
            pwr_enable <= 1'b1;
        end else begin
            iso_en <= 1'b0;
            pwr_enable <= 1'b0;
...
functional details 
[stderr]
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.\n/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260425_215014_451219_c08f66 ok ok failed skipped failed functional /workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260425_215014_451219_c08f66__sample_4
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output reg [31:0] data_out
);

    // Instantiate the AON Controller
    aon_ctrl aon_ctrl_inst(.clk(clk), .rst_n(rst_n), .sleep_req(sleep_req));

    // Instantiate the DSP Domain
    pd_dsp pd_dsp_inst(.clk(clk), .data_in(data_in), .data_out(data_out));

endmodule

module aon_ctrl(
    input clk,
    input rst_n,
    input sleep_req,
    output reg pwr_enable,
    output reg iso_en
);

    always @(posedge clk) begin
        if (rst_n) begin
            pwr_enable <= 1'b1;
            iso_en <= 1'b0;
        end else begin
            if (sleep_req) begin
                iso_en <= 1'b1;
                pwr_enable <= 1'b1;
...
functional details 
[stderr]
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.\n/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260425_215014_451219_c08f66 ok failed failed skipped failed syntax /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `soc_top.aon_ctrl_inst'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260425_215014_451219_c08f66__sample_5
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output reg [31:0] data_out
);

    // UPF Control Hooks
    output reg pwr_enable;
    output reg iso_en;

    // Submodules
    aon_ctrl aon_ctrl_inst(.sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
    pd_dsp pd_dsp_inst(.clk(clk), .data_in(data_in), .data_out(data_out));

endmodule

module aon_ctrl(
    input sleep_req,
    output reg pwr_enable,
    output reg iso_en
);

    always @(posedge clk) begin
        if (sleep_req) begin
            iso_en <= 1'b1;
            pwr_enable <= 1'b1;
        end else begin
            iso_en <= 1'b0;
            pwr_enable <= 1'b0;
        end
...
syntax details 
[stderr]
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `soc_top.aon_ctrl_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:14: error: expression not valid in assign l-value: &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:44: error: Unable to bind wire/reg/memory `reset' in `soc_top.pd_dsp_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:44: error: Unable to elaborate condition expression.
6 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `tb_task_34.dut.aon_ctrl_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:14: error: expression not valid in assign l-value: &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:44: error: Unable to bind wire/reg/memory `reset' in `tb_task_34.dut.pd_dsp_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:44: error: Unable to elaborate condition expression.
8 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `soc_top.aon_ctrl_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:14: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:44: error: Unable to bind wire/reg/memory `reset' in `soc_top.pd_dsp_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/generated.v:44: error: Unable to elaborate condition expression.\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.\n/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `tb_task_34.dut.aon_ctrl_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:14: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:44: error: Unable to bind wire/reg/memory `reset' in `tb_task_34.dut.pd_dsp_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:44: error: Unable to elaborate condition expression.\n8 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260425_215014_451219_c08f66 ok failed failed skipped failed syntax /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `soc_top.aon_ctrl_inst'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260425_215014_451219_c08f66__sample_6
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output reg [31:0] data_out
);

    // Power domain control signals
    reg pwr_enable;
    reg iso_en;

    // Instantiate submodules
    aon_ctrl aon_ctrl_inst(.sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
    pd_dsp pd_dsp_inst(.clk(clk), .data_in(data_in), .data_out(data_out));

endmodule

module aon_ctrl(
    input sleep_req,
    output reg pwr_enable,
    output reg iso_en
);

    always @(posedge clk) begin
        if (sleep_req) begin
            iso_en <= 1'b1;
            pwr_enable <= 1'b1;
        end else begin
            iso_en <= 1'b0;
            pwr_enable <= 1'b0;
        end
...
syntax details 
[stderr]
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `soc_top.aon_ctrl_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:14: error: expression not valid in assign l-value: &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)
4 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `tb_task_34.dut.aon_ctrl_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:14: error: expression not valid in assign l-value: &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)
6 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `soc_top.aon_ctrl_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:14: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.\n/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `tb_task_34.dut.aon_ctrl_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:14: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_6/functional/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260425_215014_451219_c08f66 ok failed failed skipped failed syntax /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:26: error: Unable to bind wire/reg/memory `rst_n' in `soc_top.aon_ctrl_inst'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260425_215014_451219_c08f66__sample_7
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output reg [31:0] data_out
);

    // Power domain control signals
    reg pwr_enable;
    reg iso_en;

    // Instantiate submodules
    aon_ctrl aon_ctrl_inst(.sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
    pd_dsp pd_dsp_inst(.clk(clk), .data_in(data_in), .data_out(data_out));

endmodule

module aon_ctrl(
    input sleep_req,
    output reg pwr_enable,
    output reg iso_en
);

    always @(posedge clk or posedge rst_n) begin
        if (rst_n) begin
            pwr_enable <= 1'b1;
            iso_en <= 1'b0;
        end else begin
            if (sleep_req) begin
                iso_en <= 1'b1;
                pwr_enable <= 1'b1;
...
syntax details 
[stderr]
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:26: error: Unable to bind wire/reg/memory `rst_n' in `soc_top.aon_ctrl_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:26: error: Unable to elaborate condition expression.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:14: error: expression not valid in assign l-value: &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)
4 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:26: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_34.dut.aon_ctrl_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:26: error: Unable to elaborate condition expression.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:14: error: expression not valid in assign l-value: &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)
6 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:26: error: Unable to bind wire/reg/memory `rst_n' in `soc_top.aon_ctrl_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:26: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:14: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.\n/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:26: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_34.dut.aon_ctrl_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:26: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:14: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260425_215014_451219_c08f66 ok failed failed skipped failed syntax /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `soc_top.aon_ctrl_inst'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260425_215014_451219_c08f66__sample_8
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output reg [31:0] data_out
);

    // UPF Control Hooks
    output reg pwr_enable;
    output reg iso_en;

    // Submodules
    aon_ctrl aon_ctrl_inst(.sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
    pd_dsp pd_dsp_inst(.clk(clk), .data_in(data_in), .data_out(data_out));

endmodule

module aon_ctrl(
    input sleep_req,
    output reg pwr_enable,
    output reg iso_en
);

    always @(posedge clk) begin
        if (sleep_req) begin
            iso_en <= 1'b1;
            pwr_enable <= 1'b1;
        end else begin
            iso_en <= 1'b0;
            pwr_enable <= 1'b0;
        end
...
syntax details 
[stderr]
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `soc_top.aon_ctrl_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:14: error: expression not valid in assign l-value: &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:44: error: Unable to bind wire/reg/memory `reset' in `soc_top.pd_dsp_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:44: error: Unable to elaborate condition expression.
6 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `tb_task_34.dut.aon_ctrl_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:14: error: expression not valid in assign l-value: &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:44: error: Unable to bind wire/reg/memory `reset' in `tb_task_34.dut.pd_dsp_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:44: error: Unable to elaborate condition expression.
8 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `soc_top.aon_ctrl_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:14: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:44: error: Unable to bind wire/reg/memory `reset' in `soc_top.pd_dsp_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/generated.v:44: error: Unable to elaborate condition expression.\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.\n/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `tb_task_34.dut.aon_ctrl_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:14: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:44: error: Unable to bind wire/reg/memory `reset' in `tb_task_34.dut.pd_dsp_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_8/functional/generated.v:44: error: Unable to elaborate condition expression.\n8 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260425_215014_451219_c08f66 ok failed failed skipped failed syntax /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/generated.v:20: error: iso_en Unable to assign to unresolved wires.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260425_215014_451219_c08f66__sample_9
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output reg [31:0] data_out
);

    // Power domains
    aon_ctrl aon(.sleep_req(sleep_req), .pwr_enable(pwr_enable), .iso_en(iso_en));
    pd_dsp dsp(.clk(clk), .data_in(data_in), .data_out(data_out));

    // UPF Control Hooks
    output reg pwr_enable;
    output reg iso_en;

    // Power sequencing logic
    always @(posedge clk) begin
        if (sleep_req) begin
            iso_en <= 1'b1;
            pwr_enable <= 1'b1;
            #1;
            iso_en <= 1'b0;
            pwr_enable <= 1'b0;
        end else begin
            iso_en <= 1'b0;
            pwr_enable <= 1'b1;
        end
    end
endmodule

module aon_ctrl(
...
syntax details 
[stderr]
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/generated.v:20: error: iso_en Unable to assign to unresolved wires.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/generated.v:21: error: pwr_enable Unable to assign to unresolved wires.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/generated.v:23: error: iso_en Unable to assign to unresolved wires.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/generated.v:24: error: pwr_enable Unable to assign to unresolved wires.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/generated.v:26: error: iso_en Unable to assign to unresolved wires.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/generated.v:27: error: pwr_enable Unable to assign to unresolved wires.
6 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:20: error: iso_en Unable to assign to unresolved wires.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:21: error: pwr_enable Unable to assign to unresolved wires.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:23: error: iso_en Unable to assign to unresolved wires.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:24: error: pwr_enable Unable to assign to unresolved wires.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:26: error: iso_en Unable to assign to unresolved wires.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:27: error: pwr_enable Unable to assign to unresolved wires.
warning: Found both default and explicit timescale based delays. Use
       : -Wtimescale to find the design element(s) with no explicit
       : timescale.
8 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/generated.v:20: error: iso_en Unable to assign to unresolved wires.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/generated.v:21: error: pwr_enable Unable to assign to unresolved wires.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/generated.v:23: error: iso_en Unable to assign to unresolved wires.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/generated.v:24: error: pwr_enable Unable to assign to unresolved wires.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/generated.v:26: error: iso_en Unable to assign to unresolved wires.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/generated.v:27: error: pwr_enable Unable to assign to unresolved wires.\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.\n/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:20: error: iso_en Unable to assign to unresolved wires.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:21: error: pwr_enable Unable to assign to unresolved wires.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:23: error: iso_en Unable to assign to unresolved wires.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:24: error: pwr_enable Unable to assign to unresolved wires.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:26: error: iso_en Unable to assign to unresolved wires.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:27: error: pwr_enable Unable to assign to unresolved wires.\nwarning: Found both default and explicit timescale based delays. Use\n       : -Wtimescale to find the design element(s) with no explicit\n       : timescale.\n8 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260425_215014_451219_c08f66 ok failed failed skipped failed syntax /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `soc_top.aon_ctrl_inst'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260425_215014_451219_c08f66__sample_10
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output reg [31:0] data_out
);

    // Power domain control signals
    reg pwr_enable;
    reg iso_en;

    // Instantiate submodules
    aon_ctrl aon_ctrl_inst(.sleep_req(sleep_req), .pwr_enable(&pwr_enable), .iso_en(&iso_en));
    pd_dsp pd_dsp_inst(.clk(clk), .data_in(data_in), .data_out(data_out), .iso_en(iso_en));

endmodule

module aon_ctrl(
    input sleep_req,
    output reg pwr_enable,
    output reg iso_en
);

    always @(posedge clk) begin
        if (sleep_req) begin
            iso_en <= 1'b1;
            pwr_enable <= 1'b1;
        end else begin
            iso_en <= 1'b0;
            pwr_enable <= 1'b0;
        end
...
syntax details 
[stderr]
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `soc_top.aon_ctrl_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:14: error: expression not valid in assign l-value: &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)
4 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.
/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `tb_task_34.dut.aon_ctrl_inst'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:14: error: expression not valid in assign l-value: &(iso_en)
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:14: error: Output port expression must support continuous assignment.
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)
6 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `soc_top.aon_ctrl_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:14: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)\n4 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``pwr_enable'' is not a port of dut.\n/workspace/banchmarks/pashencev/03_low_power_design/task_34/tb.v:16: error: port ``iso_en'' is not a port of dut.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:25: error: Unable to bind wire/reg/memory `clk' in `tb_task_34.dut.aon_ctrl_inst'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:25: error: Failed to evaluate event expression 'posedge clk'.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:14: error: expression not valid in assign l-value: &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:14:      : Port 2 (pwr_enable) of aon_ctrl is connected to &(pwr_enable)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:14: error: expression not valid in assign l-value: &(iso_en)\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:14: error: Output port expression must support continuous assignment.\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__03_low_power_design__task_34/sample_10/functional/generated.v:14:      : Port 3 (iso_en) of aon_ctrl is connected to &(iso_en)\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}