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codegemma:7b | RAG on

06_reset_domain_crossing / task_60 | reset_sync_2ff

benchmarkilyasov
task_idilyasov/06_reset_domain_crossing/task_60
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260425_215014_451219_c08f66

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260425_215014_451219_c08f66__sample_1
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            srst_n <= 1'b0;
        end else begin
            if (srst_n == 1'b0) begin
                srst_n <= 1'b1;
            end
        end
    end

endmodule
functional details 
[stdout]
ERROR: local reset deasserted after only one clock edge.
ERROR: restart sequence released reset too early after one edge.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260425_215014_451219_c08f66__sample_2
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            srst_n <= 1'b0;
        end else begin
            if (srst_n == 1'b0) begin
                srst_n <= 1'b1;
            end
        end
    end

endmodule
functional details 
[stdout]
ERROR: local reset deasserted after only one clock edge.
ERROR: restart sequence released reset too early after one edge.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260425_215014_451219_c08f66__sample_3
generated.v preview 
module reset_sync_2ff (
  input clk,
  input arst_n,
  output reg srst_n
);

  always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
      srst_n <= 1'b0;
    end else begin
      if (srst_n == 1'b0) begin
        srst_n <= 1'b1;
      end
    end
  end

endmodule
functional details 
[stdout]
ERROR: local reset deasserted after only one clock edge.
ERROR: restart sequence released reset too early after one edge.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260425_215014_451219_c08f66 ok failed failed skipped failed syntax /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_4/generated.v:8: error: Unable to bind wire/reg/memory `rst_n' in `reset_sync_2ff'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260425_215014_451219_c08f66__sample_4
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

    always @(posedge clk or negedge arst_n) begin
        if (rst_n == 0) begin
            srst_n <= 1'b0;
        end else begin
            if (srst_n == 1'b0) begin
                srst_n <= 1'b1;
            end
        end
    end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_4/generated.v:8: error: Unable to bind wire/reg/memory `rst_n' in `reset_sync_2ff'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_4/generated.v:8: error: Unable to elaborate condition expression.
Elaboration failed
functional details 
[stderr]
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_4/functional/generated.v:8: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_60.dut'
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_4/functional/generated.v:8: error: Unable to elaborate condition expression.
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_4/generated.v:8: error: Unable to bind wire/reg/memory `rst_n' in `reset_sync_2ff'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_4/generated.v:8: error: Unable to elaborate condition expression.\nElaboration failed\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_4/functional/generated.v:8: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_60.dut'\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_4/functional/generated.v:8: error: Unable to elaborate condition expression.\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260425_215014_451219_c08f66 ok failed failed skipped failed syntax /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_5/generated.v:10: syntax error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260425_215014_451219_c08f66__sample_5
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

    always @(posedge clk or negedge arst_n) begin
        if (arst_n == 1'b0) begin
            srst_n <= 1'b0;
        end else if (posedge clk) begin
            srst_n <= 1'b1;
        end
    end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_5/generated.v:10: syntax error
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_5/generated.v:10: error: Malformed conditional expression.
functional details 
[stderr]
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_5/functional/generated.v:10: syntax error
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_5/functional/generated.v:10: error: Malformed conditional expression.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_5/generated.v:10: syntax error\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_5/generated.v:10: error: Malformed conditional expression.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_5/functional/generated.v:10: syntax error\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_5/functional/generated.v:10: error: Malformed conditional expression.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260425_215014_451219_c08f66__sample_6
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

    always @(posedge clk or negedge arst_n) begin
        if (arst_n == 1'b0) begin
            srst_n <= 1'b0;
        end else begin
            if (srst_n == 1'b0) begin
                srst_n <= 1'b1;
            end
        end
    end

endmodule
functional details 
[stdout]
ERROR: local reset deasserted after only one clock edge.
ERROR: restart sequence released reset too early after one edge.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260425_215014_451219_c08f66 ok failed failed skipped failed syntax /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_7/generated.v:10: syntax error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260425_215014_451219_c08f66__sample_7
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

    always @(posedge clk or negedge arst_n) begin
        if (arst_n == 1'b0) begin
            srst_n <= 1'b0;
        end else if (posedge clk) begin
            srst_n <= 1'b1;
        end
    end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_7/generated.v:10: syntax error
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_7/generated.v:10: error: Malformed conditional expression.
functional details 
[stderr]
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_7/functional/generated.v:10: syntax error
/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_7/functional/generated.v:10: error: Malformed conditional expression.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_7/generated.v:10: syntax error\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_7/generated.v:10: error: Malformed conditional expression.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_7/functional/generated.v:10: syntax error\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_60/sample_7/functional/generated.v:10: error: Malformed conditional expression.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260425_215014_451219_c08f66__sample_8
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

    always @(posedge clk or negedge arst_n) begin
        if (!arst_n) begin
            srst_n <= 1'b0;
        end else begin
            if (srst_n == 1'b0) begin
                srst_n <= 1'b1;
            end
        end
    end

endmodule
functional details 
[stdout]
ERROR: local reset deasserted after only one clock edge.
ERROR: restart sequence released reset too early after one edge.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260425_215014_451219_c08f66__sample_9
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

    always @(posedge clk or negedge arst_n) begin
        if (arst_n == 1'b0) begin
            srst_n <= 1'b0;
        end else begin
            if (srst_n == 1'b0) begin
                srst_n <= 1'b1;
            end
        end
    end

endmodule
functional details 
[stdout]
ERROR: local reset deasserted after only one clock edge.
ERROR: restart sequence released reset too early after one edge.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset was not asserted immediately.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260425_215014_451219_c08f66__sample_10
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

    // Asynchronous assertion
    always @(posedge arst_n)
        srst_n <= 1'b0;

    // Synchronous deassertion
    always @(posedge clk)
        if (srst_n == 1'b0)
            srst_n <= 1'b1;

endmodule
functional details 
[stdout]
ERROR: reset was not asserted immediately.
ERROR: local reset deasserted after only one clock edge.
ERROR: asynchronous assertion failed during active operation.
ERROR: restart sequence released reset too early after one edge.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset was not asserted immediately.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}