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codegemma:7b | RAG on

06_reset_domain_crossing / task_61 | ordered_reset_ctrl

benchmarkilyasov
task_idilyasov/06_reset_domain_crossing/task_61
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260425_215014_451219_c08f66

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260425_215014_451219_c08f66__sample_1
generated.v preview 
module ordered_reset_ctrl(
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

    // Reset synchronizer for domain A
    reg rst_a_sync;
    always @(posedge clk_a) begin
        if (arst_n == 0) begin
            rst_a_sync <= 1'b0;
        end else begin
            rst_a_sync <= rst_a_n;
        end
    end

    // Reset synchronizer for domain B
    reg rst_b_sync;
    always @(posedge clk_b) begin
        if (a_init_done == 1'b1 && rst_a_sync == 1'b0) begin
            rst_b_sync <= rst_a_sync;
        end else begin
            rst_b_sync <= 1'b1;
        end
    end

    // Output local resets
    assign rst_a_n = rst_a_sync;
    assign rst_b_n = rst_b_sync;
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B did not release after the second clk_b stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260425_215014_451219_c08f66__sample_2
generated.v preview 
module ordered_reset_ctrl(
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

    // 2-flop reset synchronizer for rst_a_n
    reg rst_a_n_sync;
    always @(posedge clk_a) begin
        rst_a_n_sync <= arst_n;
    end

    // Ready condition for domain B release
    reg ready_b;
    always @(posedge clk_a) begin
        ready_b <= a_init_done & ~rst_a_n_sync;
    end

    // 2-flop synchronizer for ready_b
    reg ready_b_sync;
    always @(posedge clk_b) begin
        ready_b_sync <= ready_b;
    end

    // rst_b_n deassertion based on synchronized ready condition
    always @(posedge clk_b) begin
        rst_b_n <= ~ready_b_sync;
    end
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B released after only one clk_b synchronizer stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260425_215014_451219_c08f66__sample_3
generated.v preview 
module ordered_reset_ctrl(
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

    // 2-flop reset synchronizer for rst_a_n
    reg rst_a_sync;
    always @(posedge clk_a) begin
        if (arst_n == 0) begin
            rst_a_sync <= 1'b0;
        end else begin
            rst_a_sync <= rst_a_n;
        end
    end

    // Ready condition for domain B release
    reg ready_b;
    always @(posedge clk_a) begin
        if (a_init_done == 1'b1 && rst_a_sync == 1'b0) begin
            ready_b <= 1'b1;
        end else begin
            ready_b <= 1'b0;
        end
    end

    // 2-flop synchronizer for ready_b
    reg ready_b_sync;
    always @(posedge clk_b) begin
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B released after only one clk_b synchronizer stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260425_215014_451219_c08f66__sample_4
generated.v preview 
module ordered_reset_ctrl(
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

    // 2-flop reset synchronizer for rst_a_n
    reg rst_a_n_sync;
    always @(posedge clk_a) begin
        rst_a_n_sync <= arst_n;
    end

    // Ready condition for domain B release
    reg ready_b;
    always @(posedge clk_a) begin
        ready_b <= a_init_done & ~rst_a_n_sync;
    end

    // 2-flop synchronizer for ready condition
    reg ready_b_sync;
    always @(posedge clk_b) begin
        ready_b_sync <= ready_b;
    end

    // rst_b_n deassertion based on synchronized ready condition
    always @(posedge clk_b) begin
        rst_b_n <= ~ready_b_sync;
    end
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B released after only one clk_b synchronizer stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260425_215014_451219_c08f66__sample_5
generated.v preview 
module ordered_reset_ctrl(
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

    // 2-flop reset synchronizer for rst_a_n
    reg rst_a_n_sync;
    always @(posedge clk_a) begin
        if (arst_n == 0) begin
            rst_a_n_sync <= 1'b0;
        end else begin
            rst_a_n_sync <= rst_a_n;
        end
    end

    // Ready condition for domain B release
    reg ready_b;
    always @(posedge clk_a) begin
        if (a_init_done == 1 && rst_a_n_sync == 1) begin
            ready_b <= 1'b1;
        end else begin
            ready_b <= 1'b0;
        end
    end

    // 2-flop synchronizer for ready_b
    reg ready_b_sync;
    always @(posedge clk_b) begin
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B released after only one clk_b synchronizer stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260425_215014_451219_c08f66__sample_6
generated.v preview 
module ordered_reset_ctrl(
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

    // 2-flop reset synchronizer for rst_a_n
    reg rst_a_n_sync;
    always @(posedge clk_a) begin
        rst_a_n_sync <= arst_n;
    end

    // Ready condition for domain B release
    reg ready_b;
    always @(posedge clk_a) begin
        if (a_init_done) begin
            ready_b <= rst_a_n_sync;
        end else begin
            ready_b <= 1'b0;
        end
    end

    // 2-flop synchronizer for ready_b
    reg ready_b_sync;
    always @(posedge clk_b) begin
        ready_b_sync <= ready_b;
    end

    // rst_b_n deassertion based on synchronized ready condition
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B did not release after the second clk_b stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260425_215014_451219_c08f66__sample_7
generated.v preview 
module ordered_reset_ctrl(
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

    // 2-flop reset synchronizer for rst_a_n
    reg rst_a_n_sync;
    always @(posedge clk_a) begin
        rst_a_n_sync <= arst_n;
    end

    // Ready condition for domain B release
    reg ready_b;
    always @(posedge clk_a) begin
        ready_b <= a_init_done & ~rst_a_n_sync;
    end

    // 2-flop synchronizer for ready_b
    reg ready_b_sync;
    always @(posedge clk_b) begin
        ready_b_sync <= ready_b;
    end

    // rst_b_n deassertion based on synchronized ready condition
    assign rst_b_n = ~ready_b_sync;

endmodule
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B released after only one clk_b synchronizer stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260425_215014_451219_c08f66__sample_8
generated.v preview 
module ordered_reset_ctrl(
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

    // 2-flop reset synchronizer for rst_a_n
    reg rst_a_sync;
    always @(posedge clk_a) begin
        if (arst_n == 0) begin
            rst_a_sync <= 1'b0;
        end else begin
            rst_a_sync <= rst_a_n;
        end
    end

    // Ready condition for domain B release
    reg ready_b;
    always @(posedge clk_a) begin
        if (a_init_done == 1'b1 && rst_a_sync == 1'b0) begin
            ready_b <= 1'b1;
        end else begin
            ready_b <= 1'b0;
        end
    end

    // 2-flop synchronizer for ready_b
    reg ready_b_sync;
    always @(posedge clk_b) begin
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B released after only one clk_b synchronizer stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260425_215014_451219_c08f66__sample_9
generated.v preview 
module ordered_reset_ctrl(
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

    // 2-flop reset synchronizer for rst_a_n
    reg rst_a_n_sync;
    always @(posedge clk_a) begin
        rst_a_n_sync <= arst_n;
    end

    // Ready condition for domain B release
    reg ready_b;
    always @(posedge clk_a) begin
        ready_b <= a_init_done & ~rst_a_n_sync;
    end

    // 2-flop synchronizer for ready_b
    reg ready_b_sync;
    always @(posedge clk_b) begin
        ready_b_sync <= ready_b;
    end

    // rst_b_n deassertion
    assign rst_b_n = ~ready_b_sync;

endmodule
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B released after only one clk_b synchronizer stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260425_215014_451219_c08f66__sample_10
generated.v preview 
module ordered_reset_ctrl(
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

    // 2-flop reset synchronizer for rst_a_n
    reg rst_a_n_sync;
    always @(posedge clk_a) begin
        rst_a_n_sync <= arst_n;
    end

    // Ready condition for domain B release
    reg ready_b;
    always @(posedge clk_a) begin
        ready_b <= a_init_done & ~rst_a_n_sync;
    end

    // 2-flop synchronizer for ready_b
    reg ready_b_sync;
    always @(posedge clk_b) begin
        ready_b_sync <= ready_b;
    end

    // rst_b_n deassertion based on synchronized ready condition
    assign rst_b_n = ~ready_b_sync;

endmodule
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B released after only one clk_b synchronizer stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}