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codegemma:7b | RAG on

06_reset_domain_crossing / task_62 | triple_reset_sequencer

benchmarkilyasov
task_idilyasov/06_reset_domain_crossing/task_62
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260425_215014_451219_c08f66

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260425_215014_451219_c08f66__sample_1
generated.v preview 
module triple_reset_sequencer(
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    reg rst_cpu_reg, rst_bus_reg, rst_periph_reg;

    always @(posedge clk_cpu) begin
        if (arst_n == 0) begin
            rst_cpu_reg <= 1'b0;
        end else begin
            rst_cpu_reg <= rst_cpu_reg;
        end
    end

    always @(posedge clk_bus) begin
        if (rst_cpu_reg == 1'b0) begin
            rst_bus_reg <= 1'b0;
        end else begin
            rst_bus_reg <= rst_bus_reg;
        end
    end

    always @(posedge clk_periph) begin
        if (rst_bus_reg == 1'b0) begin
            rst_periph_reg <= 1'b0;
        end else begin
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260425_215014_451219_c08f66__sample_2
generated.v preview 
module triple_reset_sequencer(
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    reg rst_cpu_reg, rst_bus_reg, rst_periph_reg;

    always @(posedge clk_cpu) begin
        if (arst_n == 0) begin
            rst_cpu_reg <= 1'b0;
        end else begin
            rst_cpu_reg <= rst_cpu_reg;
        end
    end

    always @(posedge clk_bus) begin
        if (rst_cpu_reg == 1'b0) begin
            rst_bus_reg <= 1'b0;
        end else begin
            rst_bus_reg <= rst_bus_reg;
        end
    end

    always @(posedge clk_periph) begin
        if (rst_bus_reg == 1'b0) begin
            rst_periph_reg <= 1'b0;
        end else begin
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260425_215014_451219_c08f66__sample_3
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    // CPU reset
    reg rst_cpu_reg;
    always @(posedge clk_cpu or posedge arst_n)
        rst_cpu_reg <= arst_n ? 1'b0 : rst_cpu_reg;
    assign rst_cpu_n = ~rst_cpu_reg;

    // Bus reset
    reg rst_bus_reg;
    always @(posedge clk_bus)
        rst_bus_reg <= rst_cpu_reg;
    assign rst_bus_n = ~rst_bus_reg;

    // Peripheral reset
    reg rst_periph_reg;
    always @(posedge clk_periph)
        rst_periph_reg <= rst_bus_reg;
    assign rst_periph_n = ~rst_periph_reg;

endmodule
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
OpenLane failed: 2
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.failed",
    "message": "OpenLane failed: 2",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260425_215014_451219_c08f66__sample_4
generated.v preview 
module triple_reset_sequencer(
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    reg rst_cpu_reg, rst_bus_reg, rst_periph_reg;

    always @(posedge clk_cpu) begin
        if (arst_n == 0) begin
            rst_cpu_reg <= 1'b0;
        end else begin
            rst_cpu_reg <= rst_cpu_reg;
        end
    end

    always @(posedge clk_bus) begin
        if (rst_cpu_reg == 1'b0) begin
            rst_bus_reg <= 1'b0;
        end else begin
            rst_bus_reg <= rst_bus_reg;
        end
    end

    always @(posedge clk_periph) begin
        if (rst_bus_reg == 1'b0) begin
            rst_periph_reg <= 1'b0;
        end else begin
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260425_215014_451219_c08f66__sample_5
generated.v preview 
module triple_reset_sequencer(
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    reg rst_cpu_reg, rst_bus_reg, rst_periph_reg;

    always @(posedge clk_cpu) begin
        if (arst_n == 0) begin
            rst_cpu_reg <= 1'b0;
        end else begin
            rst_cpu_reg <= rst_cpu_reg;
        end
    end

    always @(posedge clk_bus) begin
        if (rst_cpu_reg == 1'b0) begin
            rst_bus_reg <= 1'b0;
        end else begin
            rst_bus_reg <= rst_bus_reg;
        end
    end

    always @(posedge clk_periph) begin
        if (rst_bus_reg == 1'b0) begin
            rst_periph_reg <= 1'b0;
        end else begin
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260425_215014_451219_c08f66__sample_6
generated.v preview 
module triple_reset_sequencer(
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    reg rst_cpu_reg, rst_bus_reg, rst_periph_reg;

    always @(posedge clk_cpu) begin
        if (arst_n == 0) begin
            rst_cpu_reg <= 1'b0;
        end else begin
            rst_cpu_reg <= rst_cpu_reg;
        end
    end

    always @(posedge clk_bus) begin
        if (rst_cpu_reg == 1'b0) begin
            rst_bus_reg <= 1'b0;
        end else begin
            rst_bus_reg <= rst_bus_reg;
        end
    end

    always @(posedge clk_periph) begin
        if (rst_bus_reg == 1'b0) begin
            rst_periph_reg <= 1'b0;
        end else begin
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260425_215014_451219_c08f66__sample_7
generated.v preview 
module triple_reset_sequencer(
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    reg rst_cpu_reg, rst_bus_reg, rst_periph_reg;

    always @(posedge clk_cpu) begin
        if (arst_n == 0) begin
            rst_cpu_reg <= 1'b0;
        end else begin
            rst_cpu_reg <= rst_cpu_reg;
        end
    end

    always @(posedge clk_bus) begin
        if (rst_cpu_reg == 1'b0) begin
            rst_bus_reg <= 1'b0;
        end else begin
            rst_bus_reg <= rst_bus_reg;
        end
    end

    always @(posedge clk_periph) begin
        if (rst_bus_reg == 1'b0) begin
            rst_periph_reg <= 1'b0;
        end else begin
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260425_215014_451219_c08f66__sample_8
generated.v preview 
module triple_reset_sequencer(
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    reg rst_cpu_reg, rst_bus_reg, rst_periph_reg;
    reg rst_cpu_sync, rst_bus_sync, rst_periph_sync;

    always @(posedge clk_cpu) begin
        if (arst_n == 0) begin
            rst_cpu_reg <= 1'b0;
        end else begin
            rst_cpu_reg <= rst_cpu_reg;
        end
        rst_cpu_sync <= rst_cpu_reg;
    end

    always @(posedge clk_bus) begin
        rst_bus_sync <= rst_cpu_sync;
    end

    always @(posedge clk_periph) begin
        rst_periph_sync <= rst_bus_sync;
    end

    assign rst_cpu_n = ~rst_cpu_sync;
    assign rst_bus_n = ~rst_bus_sync;
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260425_215014_451219_c08f66__sample_9
generated.v preview 
module triple_reset_sequencer(
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    reg rst_cpu_reg, rst_bus_reg, rst_periph_reg;

    always @(posedge clk_cpu) begin
        if (arst_n == 0) begin
            rst_cpu_reg <= 1'b0;
        end else begin
            rst_cpu_reg <= rst_cpu_reg;
        end
    end

    always @(posedge clk_bus) begin
        if (rst_cpu_reg == 1'b0) begin
            rst_bus_reg <= 1'b0;
        end else begin
            rst_bus_reg <= rst_bus_reg;
        end
    end

    always @(posedge clk_periph) begin
        if (rst_bus_reg == 1'b0) begin
            rst_periph_reg <= 1'b0;
        end else begin
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260425_215014_451219_c08f66 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260425_215014_451219_c08f66__sample_10
generated.v preview 
module triple_reset_sequencer(
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

    reg rst_cpu_reg, rst_bus_reg, rst_periph_reg;

    always @(posedge clk_cpu) begin
        if (arst_n == 0) begin
            rst_cpu_reg <= 1'b0;
        end else begin
            rst_cpu_reg <= rst_cpu_reg;
        end
    end

    always @(posedge clk_bus) begin
        if (rst_cpu_reg == 1'b0) begin
            rst_bus_reg <= 1'b0;
        end else begin
            rst_bus_reg <= rst_bus_reg;
        end
    end

    always @(posedge clk_periph) begin
        if (rst_bus_reg == 1'b0) begin
            rst_periph_reg <= 1'b0;
        end else begin
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}