06_reset_domain_crossing / task_63 | delayed_reset_release
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260425_215014_451219_c08f66 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_1/generated.v:15: error: Could not find variable ``srst_n_reg'' in ``delayed_reset_release'' |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260425_215014_451219_c08f66__sample_1
generated.v previewmodule delayed_reset_release(
input clk,
input arst_n,
input [1:0] release_delay,
output srst_n,
output init_pulse
);
reg rst_n_reg;
reg [1:0] release_delay_reg;
reg init_pulse_reg;
always @(posedge clk) begin
if (arst_n == 0) begin
srst_n_reg <= 1'b0;
init_pulse_reg <= 1'b1;
release_delay_reg <= 2'b00;
end else begin
if (release_delay_reg == 2'b11) begin
srst_n_reg <= 1'b1;
init_pulse_reg <= 1'b0;
release_delay_reg <= 2'b00;
end else begin
srst_n_reg <= rst_n_reg;
init_pulse_reg <= init_pulse_reg;
release_delay_reg <= release_delay_reg + 1'b1;
end
end
end
assign srst_n = rst_n_reg;
assign init_pulse = init_pulse_reg;
...
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_1/generated.v:15: error: Could not find variable ``srst_n_reg'' in ``delayed_reset_release'' /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_1/generated.v:20: error: Could not find variable ``srst_n_reg'' in ``delayed_reset_release'' /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_1/generated.v:24: error: Could not find variable ``srst_n_reg'' in ``delayed_reset_release'' 3 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_1/functional/generated.v:15: error: Could not find variable ``srst_n_reg'' in ``tb_task_63.dut'' /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_1/functional/generated.v:20: error: Could not find variable ``srst_n_reg'' in ``tb_task_63.dut'' /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_1/functional/generated.v:24: error: Could not find variable ``srst_n_reg'' in ``tb_task_63.dut'' 3 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_1/generated.v:15: error: Could not find variable ``srst_n_reg'' in ``delayed_reset_release''\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_1/generated.v:20: error: Could not find variable ``srst_n_reg'' in ``delayed_reset_release''\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_1/generated.v:24: error: Could not find variable ``srst_n_reg'' in ``delayed_reset_release''\n3 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_1/functional/generated.v:15: error: Could not find variable ``srst_n_reg'' in ``tb_task_63.dut''\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_1/functional/generated.v:20: error: Could not find variable ``srst_n_reg'' in ``tb_task_63.dut''\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_1/functional/generated.v:24: error: Could not find variable ``srst_n_reg'' in ``tb_task_63.dut''\n3 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260425_215014_451219_c08f66 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260425_215014_451219_c08f66__sample_2
generated.v previewmodule delayed_reset_release(
input clk,
input arst_n,
input [1:0] release_delay,
output srst_n,
output init_pulse
);
reg rst_n_reg;
reg [1:0] release_delay_reg;
reg init_pulse_reg;
always @(posedge clk) begin
if (arst_n == 0) begin
rst_n_reg <= 1'b0;
release_delay_reg <= 2'b0;
init_pulse_reg <= 1'b1;
end else begin
if (rst_n_reg == 1'b0) begin
if (release_delay_reg == release_delay) begin
rst_n_reg <= 1'b1;
init_pulse_reg <= 1'b0;
end else begin
release_delay_reg <= release_delay_reg + 1'b1;
end
end
end
end
assign srst_n = rst_n_reg;
assign init_pulse = init_pulse_reg;
...
functional details[stdout] ERROR: outputs were not properly reset. ERROR: reset released before the extra delay window started. ERROR: extra hold cycle 1 failed. ERROR: extra hold cycle 2 failed. ERROR: reset did not release with a one-cycle init pulse after the full delay. ERROR: asynchronous reassertion failed. ERROR: delay=0 still requires the base synchronizer and should stay low after one edge. ERROR: delay=0 did not release immediately after the base synchronizer completed. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260425_215014_451219_c08f66 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260425_215014_451219_c08f66__sample_3
generated.v previewmodule delayed_reset_release(
input clk,
input arst_n,
input [1:0] release_delay,
output srst_n,
output init_pulse
);
reg rst_n_reg;
reg [1:0] release_delay_reg;
reg init_pulse_reg;
always @(posedge clk) begin
if (arst_n == 0) begin
rst_n_reg <= 1'b0;
release_delay_reg <= 2'b00;
init_pulse_reg <= 1'b1;
end else begin
if (rst_n_reg == 1'b0) begin
if (release_delay_reg == release_delay) begin
rst_n_reg <= 1'b1;
init_pulse_reg <= 1'b0;
end else begin
release_delay_reg <= release_delay_reg + 1'b1;
end
end
end
end
assign srst_n = rst_n_reg;
assign init_pulse = init_pulse_reg;
...
functional details[stdout] ERROR: outputs were not properly reset. ERROR: reset released before the extra delay window started. ERROR: extra hold cycle 1 failed. ERROR: extra hold cycle 2 failed. ERROR: reset did not release with a one-cycle init pulse after the full delay. ERROR: asynchronous reassertion failed. ERROR: delay=0 still requires the base synchronizer and should stay low after one edge. ERROR: delay=0 did not release immediately after the base synchronizer completed. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260425_215014_451219_c08f66 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260425_215014_451219_c08f66__sample_4
generated.v previewmodule delayed_reset_release(
input clk,
input arst_n,
input [1:0] release_delay,
output srst_n,
output init_pulse
);
reg rst_n_reg;
reg [1:0] release_delay_reg;
reg init_pulse_reg;
always @(posedge clk) begin
if (arst_n == 0) begin
rst_n_reg <= 1'b0;
release_delay_reg <= 2'b0;
init_pulse_reg <= 1'b1;
end else begin
if (rst_n_reg == 1'b0) begin
if (release_delay_reg == release_delay) begin
rst_n_reg <= 1'b1;
init_pulse_reg <= 1'b0;
end else begin
release_delay_reg <= release_delay_reg + 1;
end
end
end
end
assign srst_n = rst_n_reg;
assign init_pulse = init_pulse_reg;
...
functional details[stdout] ERROR: outputs were not properly reset. ERROR: reset released before the extra delay window started. ERROR: extra hold cycle 1 failed. ERROR: extra hold cycle 2 failed. ERROR: reset did not release with a one-cycle init pulse after the full delay. ERROR: asynchronous reassertion failed. ERROR: delay=0 still requires the base synchronizer and should stay low after one edge. ERROR: delay=0 did not release immediately after the base synchronizer completed. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260425_215014_451219_c08f66 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260425_215014_451219_c08f66__sample_5
generated.v previewmodule delayed_reset_release(
input clk,
input arst_n,
input release_delay,
output srst_n,
output init_pulse
);
reg rst_n_reg;
reg init_pulse_reg;
reg [2:0] release_delay_reg;
always @(posedge clk) begin
if (arst_n == 1'b0) begin
rst_n_reg <= 1'b0;
init_pulse_reg <= 1'b1;
release_delay_reg <= 3'b0;
end else begin
rst_n_reg <= ~rst_n_reg;
if (rst_n_reg == 1'b0) begin
init_pulse_reg <= 1'b0;
if (release_delay_reg == 3'b0) begin
release_delay_reg <= 3'b1;
end else begin
release_delay_reg <= release_delay_reg - 1'b1;
end
end
end
end
assign srst_n = rst_n_reg;
assign init_pulse = init_pulse_reg;
...
functional details[stdout] ERROR: outputs were not properly reset. ERROR: reset released after only one synchronizer edge. ERROR: extra hold cycle 1 failed. ERROR: reset did not release with a one-cycle init pulse after the full delay. ERROR: init_pulse was not exactly one cycle wide. ERROR: delay=0 still requires the base synchronizer and should stay low after one edge. ERROR: delay=0 did not release immediately after the base synchronizer completed. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260425_215014_451219_c08f66 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_6/generated.v:27: error: Unable to bind wire/reg/memory `rst_n' in `delayed_reset_release' |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260425_215014_451219_c08f66__sample_6
generated.v previewmodule delayed_reset_release(
input clk,
input arst_n,
input release_delay,
output srst_n,
output init_pulse
);
reg rst_n_reg;
reg init_pulse_reg;
reg [2:0] release_delay_reg;
always @(posedge clk) begin
if (arst_n == 1'b0) begin
rst_n_reg <= 1'b0;
init_pulse_reg <= 1'b1;
release_delay_reg <= 3'b0;
end else begin
rst_n_reg <= rst_n_reg_sync;
init_pulse_reg <= init_pulse_reg_sync;
release_delay_reg <= release_delay_reg_sync;
end
end
reg rst_n_reg_sync;
always @(posedge clk) begin
rst_n_reg_sync <= rst_n;
end
reg init_pulse_reg_sync;
always @(posedge clk) begin
init_pulse_reg_sync <= init_pulse_reg;
...
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_6/generated.v:27: error: Unable to bind wire/reg/memory `rst_n' in `delayed_reset_release' Elaboration failed functional details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_6/functional/generated.v:27: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_63.dut' /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:14: warning: Port 3 (release_delay) of delayed_reset_release expects 1 bits, got 2. /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:14: : Pruning 1 high bits of the expression. 1 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_6/generated.v:27: error: Unable to bind wire/reg/memory `rst_n' in `delayed_reset_release'\nElaboration failed\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_6/functional/generated.v:27: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_63.dut'\n/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:14: warning: Port 3 (release_delay) of delayed_reset_release expects 1 bits, got 2.\n/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:14: : Pruning 1 high bits of the expression.\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260425_215014_451219_c08f66 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260425_215014_451219_c08f66__sample_7
generated.v previewmodule delayed_reset_release(
input clk,
input arst_n,
input [1:0] release_delay,
output srst_n,
output init_pulse
);
reg rst_n_reg;
reg [1:0] release_delay_reg;
reg init_pulse_reg;
always @(posedge clk) begin
if (arst_n == 0) begin
rst_n_reg <= 1'b0;
release_delay_reg <= 2'b0;
init_pulse_reg <= 1'b1;
end else begin
if (rst_n_reg == 1'b0) begin
if (release_delay_reg == release_delay) begin
rst_n_reg <= 1'b1;
init_pulse_reg <= 1'b0;
end else begin
release_delay_reg <= release_delay_reg + 1'b1;
end
end
end
end
assign srst_n = rst_n_reg;
assign init_pulse = init_pulse_reg;
...
functional details[stdout] ERROR: outputs were not properly reset. ERROR: reset released before the extra delay window started. ERROR: extra hold cycle 1 failed. ERROR: extra hold cycle 2 failed. ERROR: reset did not release with a one-cycle init pulse after the full delay. ERROR: asynchronous reassertion failed. ERROR: delay=0 still requires the base synchronizer and should stay low after one edge. ERROR: delay=0 did not release immediately after the base synchronizer completed. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260425_215014_451219_c08f66 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260425_215014_451219_c08f66__sample_8
generated.v previewmodule delayed_reset_release(
input clk,
input arst_n,
input [1:0] release_delay,
output srst_n,
output init_pulse
);
reg rst_n_reg;
reg [1:0] release_delay_reg;
reg init_pulse_reg;
always @(posedge clk) begin
if (arst_n == 0) begin
rst_n_reg <= 1'b0;
release_delay_reg <= 2'b0;
init_pulse_reg <= 1'b1;
end else begin
if (rst_n_reg == 1'b0) begin
if (release_delay_reg == release_delay) begin
rst_n_reg <= 1'b1;
init_pulse_reg <= 1'b0;
end else begin
release_delay_reg <= release_delay_reg + 1'b1;
end
end
end
end
assign srst_n = rst_n_reg;
assign init_pulse = init_pulse_reg;
...
functional details[stdout] ERROR: outputs were not properly reset. ERROR: reset released before the extra delay window started. ERROR: extra hold cycle 1 failed. ERROR: extra hold cycle 2 failed. ERROR: reset did not release with a one-cycle init pulse after the full delay. ERROR: asynchronous reassertion failed. ERROR: delay=0 still requires the base synchronizer and should stay low after one edge. ERROR: delay=0 did not release immediately after the base synchronizer completed. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260425_215014_451219_c08f66 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260425_215014_451219_c08f66__sample_9
generated.v previewmodule delayed_reset_release(
input clk,
input arst_n,
input [1:0] release_delay,
output srst_n,
output init_pulse
);
reg rst_n_reg;
reg [1:0] release_delay_reg;
reg init_pulse_reg;
always @(posedge clk) begin
if (arst_n == 0) begin
rst_n_reg <= 1'b0;
release_delay_reg <= 2'b0;
init_pulse_reg <= 1'b1;
end else begin
if (rst_n_reg == 1'b0) begin
if (release_delay_reg == release_delay) begin
rst_n_reg <= 1'b1;
init_pulse_reg <= 1'b0;
end else begin
release_delay_reg <= release_delay_reg + 1;
end
end
end
end
assign srst_n = rst_n_reg;
assign init_pulse = init_pulse_reg;
...
functional details[stdout] ERROR: outputs were not properly reset. ERROR: reset released before the extra delay window started. ERROR: extra hold cycle 1 failed. ERROR: extra hold cycle 2 failed. ERROR: reset did not release with a one-cycle init pulse after the full delay. ERROR: asynchronous reassertion failed. ERROR: delay=0 still requires the base synchronizer and should stay low after one edge. ERROR: delay=0 did not release immediately after the base synchronizer completed. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:118: $finish called at 106000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: outputs were not properly reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260425_215014_451219_c08f66 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_10/generated.v:27: error: Unable to bind wire/reg/memory `rst_n' in `delayed_reset_release' |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_63\samples\run_20260425_215014_451219_c08f66__sample_10
generated.v previewmodule delayed_reset_release(
input clk,
input arst_n,
input release_delay,
output srst_n,
output init_pulse
);
reg rst_n_reg;
reg init_pulse_reg;
reg [2:0] release_delay_reg;
always @(posedge clk) begin
if (arst_n == 1'b0) begin
rst_n_reg <= 1'b0;
init_pulse_reg <= 1'b1;
release_delay_reg <= 3'b0;
end else begin
rst_n_reg <= rst_n_reg_sync;
init_pulse_reg <= init_pulse_reg_sync;
release_delay_reg <= release_delay_reg_sync;
end
end
reg rst_n_reg_sync;
always @(posedge clk) begin
rst_n_reg_sync <= rst_n;
end
reg init_pulse_reg_sync;
always @(posedge clk) begin
init_pulse_reg_sync <= init_pulse_reg;
...
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_10/generated.v:27: error: Unable to bind wire/reg/memory `rst_n' in `delayed_reset_release' Elaboration failed functional details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_10/functional/generated.v:27: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_63.dut' /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:14: warning: Port 3 (release_delay) of delayed_reset_release expects 1 bits, got 2. /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:14: : Pruning 1 high bits of the expression. 1 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_10/generated.v:27: error: Unable to bind wire/reg/memory `rst_n' in `delayed_reset_release'\nElaboration failed\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__06_reset_domain_crossing__task_63/sample_10/functional/generated.v:27: error: Unable to bind wire/reg/memory `rst_n' in `tb_task_63.dut'\n/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:14: warning: Port 3 (release_delay) of delayed_reset_release expects 1 bits, got 2.\n/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_63/tb.v:14: : Pruning 1 high bits of the expression.\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|