12_cdv / task_121 | queue_credit_tracker
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260425_215014_451219_c08f66 | ok | failed | n/a | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_1/generated.v:12: syntax error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260425_215014_451219_c08f66__sample_1
generated.v previewmodule queue_credit_tracker(
input clk,
input rst,
input push,
input pop,
input flush,
output reg full,
output reg empty,
reg [3:0] cfg_limit
);
parameter MAX_DEPTH = cfg_limit + 1;
reg [3:0] count;
reg overflow_pulse;
reg underflow_pulse;
fifo_4x32 fifo(
.clk(clk),
.reset(rst),
.din(push ? 1'b1 : 1'b0),
.wr_en(push),
.rd_en(pop),
.dout(empty),
.full(full),
.empty(empty)
);
always @(posedge clk) begin
...
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_1/generated.v:12: syntax error /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_1/generated.v:1: Errors in port declarations. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_1/generated.v:12: syntax error\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_1/generated.v:1: Errors in port declarations.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": false,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260425_215014_451219_c08f66 | ok | failed | n/a | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_2/generated.v:18: error: Unable to bind parameter `cfg_limit' in `queue_credit_tracker' |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260425_215014_451219_c08f66__sample_2
generated.v previewmodule queue_credit_tracker(
input clk,
input rst,
input cfg_limit,
input push,
input pop,
input flush,
output reg busy,
output reg overflow_pulse,
output reg underflow_pulse,
output reg count
);
parameter MAX_DEPTH = cfg_limit + 1;
reg [MAX_DEPTH - 1:0] queue;
reg [MAX_DEPTH - 1:0] head;
reg [MAX_DEPTH - 1:0] tail;
reg [MAX_DEPTH - 1:0] credit;
always @(posedge clk) begin
if (rst) begin
head <= 0;
tail <= 0;
credit <= cfg_limit;
busy <= 0;
overflow_pulse <= 0;
underflow_pulse <= 0;
...
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_2/generated.v:18: error: Unable to bind parameter `cfg_limit' in `queue_credit_tracker' 1 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_2/generated.v:18: error: Unable to bind parameter `cfg_limit' in `queue_credit_tracker'\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": false,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260425_215014_451219_c08f66 | ok | failed | n/a | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_3/generated.v:12: syntax error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260425_215014_451219_c08f66__sample_3
generated.v previewmodule queue_credit_tracker(
input clk,
input rst,
input push,
input pop,
input flush,
output reg full,
output reg empty,
reg [3:0] cfg_limit
);
parameter MAX_DEPTH = cfg_limit + 1;
reg [3:0] count;
reg overflow_pulse;
reg underflow_pulse;
fifo_4x32 fifo(
.clk(clk),
.reset(rst),
.din(push ? 1'b1 : 1'b0),
.wr_en(push),
.rd_en(pop),
.dout(empty),
.full(full),
.empty(empty)
);
always @(posedge clk) begin
...
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_3/generated.v:12: syntax error /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_3/generated.v:1: Errors in port declarations. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_3/generated.v:12: syntax error\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_3/generated.v:1: Errors in port declarations.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": false,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260425_215014_451219_c08f66 | ok | failed | n/a | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_4/generated.v:18: error: Unable to bind parameter `cfg_limit' in `queue_credit_tracker' |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260425_215014_451219_c08f66__sample_4
generated.v previewmodule queue_credit_tracker(
input clk,
input rst,
input cfg_limit,
input push,
input pop,
input flush,
output reg busy,
output reg overflow_pulse,
output reg underflow_pulse,
output reg count
);
parameter MAX_DEPTH = cfg_limit + 1;
reg [MAX_DEPTH-1:0] queue;
reg [MAX_DEPTH-1:0] head;
reg [MAX_DEPTH-1:0] tail;
reg [MAX_DEPTH-1:0] credit;
always @(posedge clk) begin
if (rst) begin
head <= 0;
tail <= 0;
credit <= cfg_limit;
busy <= 0;
overflow_pulse <= 0;
underflow_pulse <= 0;
...
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_4/generated.v:18: error: Unable to bind parameter `cfg_limit' in `queue_credit_tracker' 1 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_4/generated.v:18: error: Unable to bind parameter `cfg_limit' in `queue_credit_tracker'\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": false,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260425_215014_451219_c08f66 | ok | ok | n/a | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260425_215014_451219_c08f66__sample_5
generated.v previewmodule queue_credit_tracker(
input clk,
input rst,
input push,
input pop,
input flush,
output reg busy,
output reg overflow_pulse,
output reg underflow_pulse,
output reg count
);
parameter CFG_LIMIT = 3;
reg [CFG_LIMIT:0] queue_depth;
always @(posedge clk) begin
if (rst) begin
busy <= 0;
overflow_pulse <= 0;
underflow_pulse <= 0;
count <= 0;
queue_depth <= 0;
end else begin
if (push && !busy) begin
if (queue_depth < CFG_LIMIT) begin
queue_depth <= queue_depth + 1;
busy <= 1;
end else begin
...
synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": false,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_6 | run_20260425_215014_451219_c08f66 | ok | failed | n/a | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_6/generated.v:14: error: Unable to bind parameter `cfg_limit' in `queue_credit_tracker' |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260425_215014_451219_c08f66__sample_6
generated.v previewmodule queue_credit_tracker(
input clk,
input rst,
input cfg_limit,
input push,
input pop,
input flush,
output reg busy,
output reg count
);
parameter MAX_DEPTH = cfg_limit + 1;
reg [MAX_DEPTH - 1:0] queue;
reg [MAX_DEPTH - 1:0] head;
reg [MAX_DEPTH - 1:0] tail;
reg overflow_pulse;
reg underflow_pulse;
always @(posedge clk) begin
if (rst) begin
head <= 0;
tail <= 0;
count <= 0;
overflow_pulse <= 0;
underflow_pulse <= 0;
busy <= 0;
end else begin
if (push && !overflow_pulse) begin
if (count < MAX_DEPTH - 1) begin
...
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_6/generated.v:14: error: Unable to bind parameter `cfg_limit' in `queue_credit_tracker' 1 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_6/generated.v:14: error: Unable to bind parameter `cfg_limit' in `queue_credit_tracker'\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": false,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260425_215014_451219_c08f66 | ok | ok | n/a | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260425_215014_451219_c08f66__sample_7
generated.v previewmodule queue_credit_tracker(
input clk,
input rst,
input push,
input pop,
input flush,
output reg full,
output reg empty,
output reg count
);
parameter CFG_LIMIT = 3;
reg [CFG_LIMIT:0] queue_credit;
always @(posedge clk) begin
if (rst) begin
queue_credit <= CFG_LIMIT;
full <= 0;
empty <= 1;
count <= 0;
end else begin
if (push && !full) begin
queue_credit <= queue_credit - 1;
full <= 1;
empty <= 0;
count <= count + 1;
end else if (pop && !empty) begin
queue_credit <= queue_credit + 1;
full <= 0;
...
synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": false,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_8 | run_20260425_215014_451219_c08f66 | ok | failed | n/a | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_8/generated.v:12: syntax error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260425_215014_451219_c08f66__sample_8
generated.v previewmodule queue_credit_tracker(
input clk,
input rst,
input push,
input pop,
input flush,
output reg full,
output reg empty,
reg [cfg_limit:0] count
);
// ... DUT code here ...
endmodule
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_8/generated.v:12: syntax error /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_8/generated.v:1: Errors in port declarations. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_8/generated.v:12: syntax error\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_8/generated.v:1: Errors in port declarations.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": false,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260425_215014_451219_c08f66 | ok | failed | n/a | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_9/generated.v:12: syntax error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260425_215014_451219_c08f66__sample_9
generated.v previewmodule queue_credit_tracker(
input clk,
input rst,
input push,
input pop,
input flush,
output reg full,
output reg empty,
reg [3:0] cfg_limit
);
parameter MAX_DEPTH = cfg_limit + 1;
reg [3:0] count;
reg overflow_pulse;
reg underflow_pulse;
fifo_4x32 fifo(
.clk(clk),
.reset(rst),
.din(push ? 1 : 0),
.wr_en(push),
.rd_en(pop),
.dout(full),
.empty(empty)
);
always @(posedge clk) begin
if (rst) begin
...
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_9/generated.v:12: syntax error /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_9/generated.v:1: Errors in port declarations. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_9/generated.v:12: syntax error\n/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/pashencev__12_cdv__task_121/sample_9/generated.v:1: Errors in port declarations.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": false,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260425_215014_451219_c08f66 | ok | ok | n/a | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\ilyasov\tasks\ilyasov__12_cdv__task_121\samples\run_20260425_215014_451219_c08f66__sample_10
generated.v previewmodule queue_credit_tracker(
input clk,
input rst,
input push,
input pop,
input flush,
output reg full,
output reg empty,
output reg count,
output reg overflow_pulse,
output reg underflow_pulse
);
parameter CFG_LIMIT = 3;
reg [CFG_LIMIT:0] queue_depth;
reg [CFG_LIMIT:0] queue_credit;
always @(posedge clk) begin
if (rst) begin
queue_depth <= 0;
queue_credit <= CFG_LIMIT;
end else begin
if (push && !full) begin
queue_depth <= queue_depth + 1;
queue_credit <= queue_credit - 1;
overflow_pulse <= 0;
end else if (push && full) begin
overflow_pulse <= 1;
end
...
synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": false,
"openlane_required": true,
"final_success": true,
"success": true
}
|