13_rtllm_arithmetic / task_10 | verified_radix2_div
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260425_215014_451219_c08f66 | ok | ok | failed | skipped | failed | functional | error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260425_215014_451219_c08f66__sample_1
generated.v previewmodule radix2_div(
input clk, rst, sign,
input [7:0] dividend, divisor,
input opn_valid, res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] SR;
reg NEG_DIVISOR;
reg cnt, start_cnt;
always @(posedge clk) begin
if (rst) begin
SR <= 0;
NEG_DIVISOR <= 0;
cnt <= 0;
start_cnt <= 0;
res_valid <= 0;
end else begin
if (opn_valid && !res_valid) begin
SR <= sign ? -dividend << 1 : dividend << 1;
NEG_DIVISOR <= sign ? -divisor : divisor;
cnt <= 1;
start_cnt <= 1;
end
if (start_cnt) begin
if (cnt == 8'b1000_0000) begin
cnt <= 0;
start_cnt <= 0;
result <= SR;
...
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_error",
"message": "error",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260425_215014_451219_c08f66 | ok | ok | failed | skipped | failed | functional | error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260425_215014_451219_c08f66__sample_2
generated.v previewmodule radix2_div(
input clk, rst, sign,
input [7:0] dividend, divisor,
input opn_valid, res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] SR;
reg NEG_DIVISOR;
reg cnt, start_cnt;
always @(posedge clk) begin
if (rst) begin
res_valid <= 0;
SR <= 0;
NEG_DIVISOR <= 0;
cnt <= 0;
start_cnt <= 0;
end else begin
if (opn_valid && !res_valid) begin
SR <= sign ? -dividend : dividend;
NEG_DIVISOR <= sign ? -divisor : divisor;
cnt <= 1;
start_cnt <= 1;
end
if (start_cnt) begin
if (cnt == 8'b10000000) begin
res_valid <= 1;
result <= {SR[7:0], SR[7:0]};
start_cnt <= 0;
...
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_error",
"message": "error",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260425_215014_451219_c08f66 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_3/generated.v:36: error: can not select part of scalar: NEG_DIVISOR |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260425_215014_451219_c08f66__sample_3
generated.v previewmodule radix2_div(
input clk, rst, sign,
input [7:0] dividend, divisor,
input opn_valid, res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] SR;
reg NEG_DIVISOR;
reg cnt, start_cnt;
always @(posedge clk) begin
if (rst) begin
SR <= 0;
NEG_DIVISOR <= 0;
cnt <= 0;
start_cnt <= 0;
res_valid <= 0;
end else begin
if (opn_valid && !res_valid) begin
SR <= sign ? -dividend << 1 : dividend << 1;
NEG_DIVISOR <= sign ? -divisor : divisor;
cnt <= 1;
start_cnt <= 1;
end
if (start_cnt) begin
if (cnt == 8'b10000000) begin
cnt <= 0;
start_cnt <= 0;
result <= {SR[7:0], SR[7:0]};
...
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_3/generated.v:36: error: can not select part of scalar: NEG_DIVISOR 1 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_3/functional/generated.v:36: error: can not select part of scalar: NEG_DIVISOR 1 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_3/generated.v:36: error: can not select part of scalar: NEG_DIVISOR\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_3/functional/generated.v:36: error: can not select part of scalar: NEG_DIVISOR\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260425_215014_451219_c08f66 | ok | ok | failed | skipped | failed | functional | error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260425_215014_451219_c08f66__sample_4
generated.v previewmodule radix2_div(
input clk, rst, sign,
input [7:0] dividend, divisor,
input opn_valid, res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] SR;
reg NEG_DIVISOR;
reg cnt, start_cnt;
always @(posedge clk) begin
if (rst) begin
SR <= 0;
NEG_DIVISOR <= 0;
cnt <= 0;
start_cnt <= 0;
res_valid <= 0;
end else begin
if (opn_valid && !res_valid) begin
SR <= sign ? -dividend << 1 : dividend << 1;
NEG_DIVISOR <= sign ? -divisor : divisor;
cnt <= 1;
start_cnt <= 1;
end
if (start_cnt) begin
if (cnt == 8'b1000_0000) begin
cnt <= 0;
start_cnt <= 0;
result <= {SR[7:0], SR[7:0]};
...
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_error",
"message": "error",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260425_215014_451219_c08f66 | ok | ok | failed | skipped | failed | functional | error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260425_215014_451219_c08f66__sample_5
generated.v previewmodule radix2_div(
input clk, rst, sign,
input [7:0] dividend, divisor,
input opn_valid, res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] SR;
reg NEG_DIVISOR;
reg cnt, start_cnt;
always @(posedge clk) begin
if (rst) begin
SR <= 0;
NEG_DIVISOR <= 0;
cnt <= 0;
start_cnt <= 0;
res_valid <= 0;
end else begin
if (opn_valid && !res_valid) begin
SR <= sign ? -dividend << 1 : dividend << 1;
NEG_DIVISOR <= sign ? -divisor : divisor;
cnt <= 1;
start_cnt <= 1;
end
if (start_cnt) begin
if (cnt == 8'b1000_0000) begin
cnt <= 0;
start_cnt <= 0;
result <= {SR[7:0], SR[7:0]};
...
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_error",
"message": "error",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260425_215014_451219_c08f66 | ok | ok | failed | skipped | failed | functional | error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260425_215014_451219_c08f66__sample_6
generated.v previewmodule radix2_div(
input clk, rst, sign,
input [7:0] dividend, divisor,
input opn_valid, res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] SR;
reg NEG_DIVISOR;
reg cnt, start_cnt;
always @(posedge clk) begin
if (rst) begin
SR <= 0;
NEG_DIVISOR <= 0;
cnt <= 0;
start_cnt <= 0;
res_valid <= 0;
end else begin
if (opn_valid && !res_valid) begin
SR <= sign ? -dividend : dividend;
NEG_DIVISOR <= sign ? -divisor : divisor;
cnt <= 1;
start_cnt <= 1;
end
if (start_cnt) begin
if (cnt == 8'b1000_0000) begin
cnt <= 0;
start_cnt <= 0;
result <= {SR[7:0], SR[7:0]};
...
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_error",
"message": "error",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260425_215014_451219_c08f66 | ok | ok | failed | skipped | failed | functional | error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260425_215014_451219_c08f66__sample_7
generated.v previewmodule radix2_div(
input clk, rst, sign,
input [7:0] dividend, divisor,
input opn_valid, res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] SR;
reg NEG_DIVISOR;
reg cnt, start_cnt;
always @(posedge clk) begin
if (rst) begin
SR <= 0;
NEG_DIVISOR <= 0;
cnt <= 0;
start_cnt <= 0;
res_valid <= 0;
end else begin
if (opn_valid && !res_valid) begin
SR <= sign ? -dividend : dividend;
NEG_DIVISOR <= sign ? -divisor : divisor;
cnt <= 1;
start_cnt <= 1;
end
if (start_cnt) begin
if (cnt == 8'b1000_0000) begin
SR <= SR[7:1] & ~SR[0] | SR[0] & NEG_DIVISOR;
cnt <= 0;
start_cnt <= 0;
...
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_error",
"message": "error",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260425_215014_451219_c08f66 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_8/generated.v:36: error: can not select part of scalar: NEG_DIVISOR |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260425_215014_451219_c08f66__sample_8
generated.v previewmodule radix2_div(
input clk, rst, sign,
input [7:0] dividend, divisor,
input opn_valid, res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] SR;
reg NEG_DIVISOR;
reg cnt, start_cnt;
always @(posedge clk) begin
if (rst) begin
SR <= 0;
NEG_DIVISOR <= 0;
cnt <= 0;
start_cnt <= 0;
res_valid <= 0;
end else begin
if (opn_valid && !res_valid) begin
SR <= sign ? -dividend : dividend;
NEG_DIVISOR <= sign ? -divisor : divisor;
cnt <= 1;
start_cnt <= 1;
end
if (start_cnt) begin
if (cnt == 8'b1000_0000) begin
result <= {SR[7:0], SR[7]};
cnt <= 0;
start_cnt <= 0;
...
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_8/generated.v:36: error: can not select part of scalar: NEG_DIVISOR 1 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_8/functional/generated.v:36: error: can not select part of scalar: NEG_DIVISOR 1 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_8/generated.v:36: error: can not select part of scalar: NEG_DIVISOR\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_8/functional/generated.v:36: error: can not select part of scalar: NEG_DIVISOR\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260425_215014_451219_c08f66 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_9/generated.v:36: error: can not select part of scalar: NEG_DIVISOR |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260425_215014_451219_c08f66__sample_9
generated.v previewmodule radix2_div(
input clk, rst, sign,
input [7:0] dividend, divisor,
input opn_valid, res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] SR;
reg NEG_DIVISOR;
reg cnt, start_cnt;
always @(posedge clk) begin
if (rst) begin
SR <= 0;
NEG_DIVISOR <= 0;
cnt <= 0;
start_cnt <= 0;
res_valid <= 0;
end else begin
if (opn_valid && !res_valid) begin
SR <= sign ? -dividend : dividend;
NEG_DIVISOR <= sign ? -divisor : divisor;
cnt <= 1;
start_cnt <= 1;
end
if (start_cnt) begin
if (cnt == 8'b1000_0000) begin
result[7:0] <= SR;
result[15:8] <= cnt;
res_valid <= 1;
start_cnt <= 0;
...
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_9/generated.v:36: error: can not select part of scalar: NEG_DIVISOR 1 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_9/functional/generated.v:36: error: can not select part of scalar: NEG_DIVISOR 1 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_9/generated.v:36: error: can not select part of scalar: NEG_DIVISOR\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_9/functional/generated.v:36: error: can not select part of scalar: NEG_DIVISOR\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260425_215014_451219_c08f66 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_10/generated.v:36: error: can not select part of scalar: NEG_DIVISOR |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codegemma-7b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260425_215014_451219_c08f66__sample_10
generated.v previewmodule radix2_div(
input clk, rst, sign,
input [7:0] dividend, divisor,
input opn_valid, res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] SR;
reg NEG_DIVISOR;
reg cnt, start_cnt;
always @(posedge clk) begin
if (rst) begin
SR <= 0;
NEG_DIVISOR <= 0;
cnt <= 0;
start_cnt <= 0;
res_valid <= 0;
end else begin
if (opn_valid && !res_valid) begin
SR <= sign ? -dividend : dividend;
NEG_DIVISOR <= sign ? -divisor : divisor;
cnt <= 1;
start_cnt <= 1;
end
if (start_cnt) begin
if (cnt == 8'b10000000) begin
cnt <= 0;
start_cnt <= 0;
result <= {SR[7:0], SR[7]};
...
syntax details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_10/generated.v:36: error: can not select part of scalar: NEG_DIVISOR 1 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_10/functional/generated.v:36: error: can not select part of scalar: NEG_DIVISOR 1 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_10/generated.v:36: error: can not select part of scalar: NEG_DIVISOR\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260425_215014_451219_c08f66/tmp/codegemma/rtllm__13_rtllm_arithmetic__task_10/sample_10/functional/generated.v:36: error: can not select part of scalar: NEG_DIVISOR\n1 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|