05_dft_testability / task_50 | scan_reg8
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/generated.v:41: error: data_out is not a valid l-value in scan_reg8. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_102437_171676_163c0c__sample_1
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output [7:0] data_out,
output scan_out
);
// Registers
reg [7:0] data_reg;
reg scan_out_reg;
// Reset logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_reg <= 8'b0;
scan_out_reg <= 1'b0;
end
end
// Functional mode logic
always @(posedge clk or negedge load_en) begin
if (~load_en) begin
data_reg <= data_in;
end
end
// Scan mode logic
always @(posedge clk or negedge scan_en) begin
...
syntax details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/generated.v:41: error: data_out is not a valid l-value in scan_reg8. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/generated.v:8: : data_out is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/generated.v:42: error: scan_out is not a valid l-value in scan_reg8. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/generated.v:9: : scan_out is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/generated.v:40: warning: @* found no sensitivities so it will never trigger. 2 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/functional/generated.v:41: error: data_out is not a valid l-value in tb_task_50.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/functional/generated.v:8: : data_out is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/functional/generated.v:42: error: scan_out is not a valid l-value in tb_task_50.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/functional/generated.v:9: : scan_out is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/functional/generated.v:40: warning: @* found no sensitivities so it will never trigger. 2 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/generated.v:41: error: data_out is not a valid l-value in scan_reg8.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/generated.v:8: : data_out is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/generated.v:42: error: scan_out is not a valid l-value in scan_reg8.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/generated.v:9: : scan_out is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/generated.v:40: warning: @* found no sensitivities so it will never trigger.\n2 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/functional/generated.v:41: error: data_out is not a valid l-value in tb_task_50.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/functional/generated.v:8: : data_out is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/functional/generated.v:42: error: scan_out is not a valid l-value in tb_task_50.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/functional/generated.v:9: : scan_out is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_1/functional/generated.v:40: warning: @* found no sensitivities so it will never trigger.\n2 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_1 | run_20260427_144342_055801_c17762 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_144342_055801_c17762__sample_1
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output reg [7:0] data_out,
output reg scan_out
);
// Registers
reg [7:0] data_r;
reg scan_out_r;
// Reset logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_r <= 8'b0;
scan_out_r <= 1'b0;
end else begin
// Functional mode
if (load_en && ~scan_en) begin
data_r <= data_in;
end
// Scan mode
if (scan_en) begin
scan_out_r <= data_r[7];
data_r <= {data_r[6:0], scan_in};
end
end
end
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_50/tb.v:159: $finish called at 126000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_2 | run_20260427_102437_171676_163c0c | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output reg [7:0] data_out,
output reg scan_out
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_out <= 8'b0;
scan_out <= 1'b0;
end else begin
// functional mode
if (scan_en == 1'b0 && load_en == 1'b1) begin
data_out <= data_in;
end else if (scan_en == 1'b0 && load_en == 1'b0) begin
// retain the current register value
end else begin
// scan mode
scan_out <= data_out[7];
data_out <= {data_out[6:0], scan_in};
end
end
end
endmodule
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_50/tb.v:159: $finish called at 126000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_2 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/generated.v:13: error: 'data_out' has already been declared in this scope. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_144342_055801_c17762__sample_2
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output [7:0] data_out,
output scan_out
);
// Registers
reg [7:0] data_out;
reg scan_out;
// Reset logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_out <= 8'b0;
scan_out <= 1'b0;
end
end
// Functional mode
always @(posedge clk) begin
if (load_en) begin
data_out <= data_in;
end
end
// Scan mode
always @(posedge clk) begin
...
syntax details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/generated.v:13: error: 'data_out' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/generated.v:8: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/generated.v:14: error: 'scan_out' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/generated.v:9: : It was declared here as a net. functional details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/functional/generated.v:13: error: 'data_out' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/functional/generated.v:8: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/functional/generated.v:14: error: 'scan_out' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/functional/generated.v:9: : It was declared here as a net. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/generated.v:13: error: 'data_out' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/generated.v:8: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/generated.v:14: error: 'scan_out' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/generated.v:9: : It was declared here as a net.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/functional/generated.v:13: error: 'data_out' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/functional/generated.v:8: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/functional/generated.v:14: error: 'scan_out' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_2/functional/generated.v:9: : It was declared here as a net.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:13: error: 'data_out' has already been declared in this scope. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output [7:0] data_out,
output scan_out
);
// Registers
reg [7:0] data_out;
reg [1:0] shift_count;
// Wires
wire load_en_sync = (load_en & rst_n) | (~load_en & ~rst_n);
wire scan_en_sync = (scan_en & rst_n) | (~scan_en & ~rst_n);
wire [7:0] data_in_sync = (data_in & load_en_sync) | (data_out & ~load_en_sync);
wire scan_out_sync = (data_out[7] & shift_count[1]) | (scan_in & shift_count[0]);
// Behavioral description
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_out <= 8'b0;
scan_out <= 1'b0;
shift_count <= 2'b0;
end else begin
// Functional mode
if (load_en_sync) begin
data_out <= data_in_sync;
end
...
syntax details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:13: error: 'data_out' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:8: : It was declared here as a net. functional details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/functional/generated.v:13: error: 'data_out' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/functional/generated.v:8: : It was declared here as a net. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:13: error: 'data_out' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:8: : It was declared here as a net.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/functional/generated.v:13: error: 'data_out' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/functional/generated.v:8: : It was declared here as a net.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:13: error: 'data_out' has already been declared in this scope. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_144342_055801_c17762__sample_3
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output [7:0] data_out,
output scan_out
);
// Registers
reg [7:0] data_out;
reg scan_out;
// Reset logic
always @(posedge clk) begin
if (rst_n == 1'b0) begin
data_out <= 8'b0;
scan_out <= 1'b0;
end
end
// Functional mode
always @(posedge clk) begin
if (load_en == 1'b1 && rst_n == 1'b1) begin
data_out <= data_in;
end
end
// Scan mode
always @(posedge clk) begin
...
syntax details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:13: error: 'data_out' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:8: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:14: error: 'scan_out' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:9: : It was declared here as a net. functional details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/functional/generated.v:13: error: 'data_out' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/functional/generated.v:8: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/functional/generated.v:14: error: 'scan_out' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/functional/generated.v:9: : It was declared here as a net. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:13: error: 'data_out' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:8: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:14: error: 'scan_out' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/generated.v:9: : It was declared here as a net.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/functional/generated.v:13: error: 'data_out' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/functional/generated.v:8: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/functional/generated.v:14: error: 'scan_out' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_3/functional/generated.v:9: : It was declared here as a net.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:13: error: 'data_out' has already been declared in this scope. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output [7:0] data_out,
output scan_out
);
// Registers
reg [7:0] data_out;
reg scan_out;
// Wire declarations
wire load_en_sync;
wire scan_en_sync;
wire rst_n_sync;
// Synchronizers
always @(posedge clk) begin
load_en_sync <= load_en;
scan_en_sync <= scan_en;
rst_n_sync <= rst_n;
end
// Reset logic
always @(posedge clk or negedge rst_n_sync) begin
if (~rst_n_sync) begin
data_out <= 8'b0;
scan_out <= 1'b0;
...
syntax details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:13: error: 'data_out' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:8: : It was declared here as a net. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:14: error: 'scan_out' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:9: : It was declared here as a net. functional details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:13: error: 'data_out' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:8: : It was declared here as a net. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:14: error: 'scan_out' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:9: : It was declared here as a net. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:13: error: 'data_out' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:8: : It was declared here as a net.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:14: error: 'scan_out' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:9: : It was declared here as a net.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:13: error: 'data_out' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:8: : It was declared here as a net.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:14: error: 'scan_out' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:9: : It was declared here as a net.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:25: error: load_en_sync is not a valid l-value in scan_reg8. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_144342_055801_c17762__sample_4
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output [7:0] data_out,
output scan_out
);
// Registers
reg [7:0] data_reg;
reg [7:0] shifted_data;
reg scan_out_reg;
// Wire declarations
wire load_en_sync;
wire scan_en_sync;
wire clk_rising_edge;
// Synchronizers
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
load_en_sync <= 1'b0;
scan_en_sync <= 1'b0;
end else begin
load_en_sync <= load_en;
scan_en_sync <= scan_en;
end
end
...
syntax details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:25: error: load_en_sync is not a valid l-value in scan_reg8. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:18: : load_en_sync is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:26: error: scan_en_sync is not a valid l-value in scan_reg8. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:19: : scan_en_sync is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:28: error: load_en_sync is not a valid l-value in scan_reg8. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:18: : load_en_sync is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:29: error: scan_en_sync is not a valid l-value in scan_reg8. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:19: : scan_en_sync is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:35: error: clk_rising_edge is not a valid l-value in scan_reg8. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:20: : clk_rising_edge is declared here as wire. Elaboration failed functional details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:25: error: load_en_sync is not a valid l-value in tb_task_50.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:18: : load_en_sync is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:26: error: scan_en_sync is not a valid l-value in tb_task_50.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:19: : scan_en_sync is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:28: error: load_en_sync is not a valid l-value in tb_task_50.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:18: : load_en_sync is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:29: error: scan_en_sync is not a valid l-value in tb_task_50.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:19: : scan_en_sync is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:35: error: clk_rising_edge is not a valid l-value in tb_task_50.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:20: : clk_rising_edge is declared here as wire. 5 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:25: error: load_en_sync is not a valid l-value in scan_reg8.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:18: : load_en_sync is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:26: error: scan_en_sync is not a valid l-value in scan_reg8.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:19: : scan_en_sync is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:28: error: load_en_sync is not a valid l-value in scan_reg8.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:18: : load_en_sync is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:29: error: scan_en_sync is not a valid l-value in scan_reg8.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:19: : scan_en_sync is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:35: error: clk_rising_edge is not a valid l-value in scan_reg8.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/generated.v:20: : clk_rising_edge is declared here as wire.\nElaboration failed\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:25: error: load_en_sync is not a valid l-value in tb_task_50.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:18: : load_en_sync is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:26: error: scan_en_sync is not a valid l-value in tb_task_50.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:19: : scan_en_sync is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:28: error: load_en_sync is not a valid l-value in tb_task_50.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:18: : load_en_sync is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:29: error: scan_en_sync is not a valid l-value in tb_task_50.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:19: : scan_en_sync is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:35: error: clk_rising_edge is not a valid l-value in tb_task_50.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__05_dft_testability__task_50/sample_4/functional/generated.v:20: : clk_rising_edge is declared here as wire.\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/generated.v:27: error: data_out is not a valid l-value in scan_reg8. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_102437_171676_163c0c__sample_5
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output [7:0] data_out,
output scan_out
);
// Registers
reg [7:0] data_reg;
reg scan_out_reg;
// Reset logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_reg <= 8'b0;
scan_out_reg <= 1'b0;
end
end
// Functional mode logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_out <= 8'b0;
end else if (load_en) begin
data_out <= data_in;
end
end
...
syntax details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/generated.v:27: error: data_out is not a valid l-value in scan_reg8. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/generated.v:8: : data_out is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/generated.v:29: error: data_out is not a valid l-value in scan_reg8. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/generated.v:8: : data_out is declared here as wire. 2 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/functional/generated.v:27: error: data_out is not a valid l-value in tb_task_50.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/functional/generated.v:8: : data_out is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/functional/generated.v:29: error: data_out is not a valid l-value in tb_task_50.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/functional/generated.v:8: : data_out is declared here as wire. 2 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/generated.v:27: error: data_out is not a valid l-value in scan_reg8.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/generated.v:8: : data_out is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/generated.v:29: error: data_out is not a valid l-value in scan_reg8.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/generated.v:8: : data_out is declared here as wire.\n2 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/functional/generated.v:27: error: data_out is not a valid l-value in tb_task_50.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/functional/generated.v:8: : data_out is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/functional/generated.v:29: error: data_out is not a valid l-value in tb_task_50.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_5/functional/generated.v:8: : data_out is declared here as wire.\n2 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_144342_055801_c17762 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_144342_055801_c17762__sample_5
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output [7:0] data_out,
output scan_out
);
// Registers
reg [7:0] data_r;
reg scan_out_r;
// Reset logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_r <= 8'b0;
scan_out_r <= 1'b0;
end else begin
// Functional mode
if (load_en) begin
data_r <= data_in;
end
// Scan mode
if (scan_en) begin
scan_out_r <= data_r[7];
data_r <= {data_r[6:0], scan_in};
end
end
end
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_50/tb.v:159: $finish called at 126000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_6 | run_20260427_102437_171676_163c0c | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output reg [7:0] data_out,
output reg scan_out
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_out <= 8'b0;
scan_out <= 1'b0;
end else begin
// functional mode
if (scan_en == 0 && load_en == 1) begin
data_out <= data_in;
end
// scan mode
if (scan_en == 1) begin
scan_out <= data_out[7];
data_out <= {data_out[6:0], scan_in};
end
end
end
endmodule
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_50/tb.v:159: $finish called at 126000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_6 | run_20260427_144342_055801_c17762 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: functional load failed. Expected A5, got 00 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_144342_055801_c17762__sample_6
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output reg [7:0] data_out,
output reg scan_out
);
// Registers
reg [7:0] data_reg;
reg [7:0] shifted_data;
reg scan_out_reg;
// Reset logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_reg <= 8'b0;
shifted_data <= 8'b0;
scan_out_reg <= 1'b0;
end else begin
// Functional mode
if (load_en) begin
data_reg <= data_in;
end
// Scan mode
if (scan_en) begin
shifted_data <= {shifted_data[6:0], scan_in};
scan_out_reg <= shifted_data[7];
...
functional details[stdout] ERROR: functional load failed. Expected A5, got 00 ERROR: register did not hold value in functional mode. ERROR: wrong first shifted-out bit. Expected 1, got 0 ERROR: wrong third shifted-out bit. Expected 1, got 0 ERROR: wrong sixth shifted-out bit. Expected 1, got 0 ERROR: wrong eighth shifted-out bit. Expected 1, got 0 ERROR: scan load failed. Expected 3C after shifting, got 1e ERROR: functional recovery after scan mode failed. Expected 5A, got ff TEST_FAILED /workspace/banchmarks/pashencev/05_dft_testability/task_50/tb.v:159: $finish called at 126000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: functional load failed. Expected A5, got 00",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: wrong second shifted-out bit. Expected 0, got 1 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output [7:0] data_out,
output scan_out
);
// Registers
reg [7:0] data_r;
reg [7:0] data_next;
reg scan_out_r;
// Combinational logic
always @* begin
// Default values
data_next = data_r;
scan_out_r = 1'b0;
// Scan mode
if (scan_en) begin
// Shift operation
data_next[6:0] = {data_r[5:0], scan_in};
scan_out_r = data_r[7];
end else begin
// Functional mode
if (load_en) begin
data_next = data_in;
end
...
functional details[stdout] ERROR: wrong second shifted-out bit. Expected 0, got 1 ERROR: wrong fourth shifted-out bit. Expected 0, got 1 ERROR: wrong fifth shifted-out bit. Expected 0, got 1 ERROR: wrong seventh shifted-out bit. Expected 0, got 1 ERROR: scan load failed. Expected 3C after shifting, got bc TEST_FAILED /workspace/banchmarks/pashencev/05_dft_testability/task_50/tb.v:159: $finish called at 126000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: wrong second shifted-out bit. Expected 0, got 1",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_144342_055801_c17762 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_144342_055801_c17762__sample_7
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output reg [7:0] data_out,
output reg scan_out
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_out <= 8'b0;
scan_out <= 1'b0;
end else begin
if (scan_en) begin
// Scan mode
scan_out <= data_out[7];
data_out <= {data_out[6:0], scan_in};
end else begin
// Functional mode
if (load_en) begin
data_out <= data_in;
end
end
end
end
endmodule
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_50/tb.v:159: $finish called at 126000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_8 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: wrong second shifted-out bit. Expected 0, got 1 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output [7:0] data_out,
output scan_out
);
// Registers
reg [7:0] data_reg;
reg [7:0] shifted_data;
wire [7:0] prev_data_out = data_reg[6:0];
// Logic for functional mode
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_reg <= 8'b0;
end else begin
if (load_en) begin
data_reg <= data_in;
end
end
end
// Logic for scan mode
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
shifted_data <= 8'b0;
end else begin
...
functional details[stdout] ERROR: wrong second shifted-out bit. Expected 0, got 1 ERROR: wrong fourth shifted-out bit. Expected 0, got 1 ERROR: wrong fifth shifted-out bit. Expected 0, got 1 ERROR: wrong seventh shifted-out bit. Expected 0, got 1 ERROR: scan load failed. Expected 3C after shifting, got ff TEST_FAILED /workspace/banchmarks/pashencev/05_dft_testability/task_50/tb.v:159: $finish called at 126000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: wrong second shifted-out bit. Expected 0, got 1",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260427_144342_055801_c17762 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_144342_055801_c17762__sample_8
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output reg [7:0] data_out,
output reg scan_out
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_out <= 8'b0;
scan_out <= 1'b0;
end else begin
// functional mode
if (scan_en == 0 && load_en == 1) begin
data_out <= data_in;
end else if (scan_en == 0 && load_en == 0) begin
// retain current register value
end else begin
// scan mode
scan_out <= data_out[7];
data_out <= {data_out[6:0], scan_in};
end
end
end
endmodule
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_50/tb.v:159: $finish called at 126000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_9 | run_20260427_102437_171676_163c0c | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output reg [7:0] data_out,
output reg scan_out
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_out <= 8'b0;
scan_out <= 1'b0;
end else begin
if (scan_en) begin
// Scan mode
scan_out <= data_out[7];
data_out <= {data_out[6:0], scan_in};
end else begin
// Functional mode
if (load_en) begin
data_out <= data_in;
end
end
end
end
endmodule
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_50/tb.v:159: $finish called at 126000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_9 | run_20260427_144342_055801_c17762 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_144342_055801_c17762__sample_9
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output reg [7:0] data_out,
output reg scan_out
);
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_out <= 8'b0;
scan_out <= 1'b0;
end else begin
if (scan_en) begin
// Scan mode
scan_out <= data_out[7];
data_out <= {data_out[6:0], scan_in};
end else begin
// Functional mode
if (load_en) begin
data_out <= data_in;
end
end
end
end
endmodule
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_50/tb.v:159: $finish called at 126000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_10 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_10/generated.v:20: syntax error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output [7:0] data_out,
output scan_out
);
// Registers
reg [7:0] data_reg;
reg [7:0] prev_data_reg;
reg scan_out_reg;
// Wire declarations
wire load_en_sync = load_en & ~rst_n;
wire scan_en_sync = scan_en & ~rst_n;
wire clk_rising = clk & ~clk'prev;
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
data_reg <= 8'b0;
prev_data_reg <= 8'b0;
scan_out_reg <= 1'b0;
end else begin
// Functional mode
if (load_en_sync) begin
data_reg <= data_in;
end else begin
data_reg <= data_reg;
...
syntax details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_10/generated.v:20: syntax error /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_10/generated.v:20: error: Invalid module item. functional details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_10/functional/generated.v:20: syntax error /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_10/functional/generated.v:20: error: Invalid module item. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_10/generated.v:20: syntax error\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_10/generated.v:20: error: Invalid module item.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_10/functional/generated.v:20: syntax error\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__05_dft_testability__task_50/sample_10/functional/generated.v:20: error: Invalid module item.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260427_144342_055801_c17762 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: asynchronous reset did not clear the scan register. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_50\samples\run_20260427_144342_055801_c17762__sample_10
generated.v previewmodule scan_reg8 (
input clk,
input rst_n,
input scan_en,
input scan_in,
input load_en,
input [7:0] data_in,
output reg [7:0] data_out,
output reg scan_out
);
// Registers for storing the current register value and previous shifted value
reg [7:0] curr_val;
reg [7:0] prev_val;
always @(posedge clk) begin
if (rst_n == 1'b0) begin
// Reset the register values to 0
curr_val <= 8'b0;
prev_val <= 8'b0;
end else begin
// In functional mode, capture data_in into data_out on rising edge of clk when load_en is high
if (load_en == 1'b1) begin
curr_val <= data_in;
end
// In scan mode, perform one shift operation on every rising edge of clk
if (scan_en == 1'b1) begin
prev_val <= curr_val[7];
curr_val <= {curr_val[6:0], scan_in};
end
end
...
functional details[stdout] ERROR: asynchronous reset did not clear the scan register. TEST_FAILED /workspace/banchmarks/pashencev/05_dft_testability/task_50/tb.v:159: $finish called at 126000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: asynchronous reset did not clear the scan register.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|