06_reset_domain_crossing / task_62 | triple_reset_sequencer
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_102437_171676_163c0c__sample_1
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync1 = 0;
reg cpu_rst_sync2 = 0;
always @(posedge clk_cpu) begin
if (arst_n == 0) begin
cpu_rst_sync1 <= 0;
cpu_rst_sync2 <= 0;
end else begin
cpu_rst_sync1 <= cpu_rst_sync2;
cpu_rst_sync2 <= arst_n;
end
end
assign rst_cpu_n = ~(cpu_rst_sync1 | cpu_rst_sync2);
// BUS reset synchronizer
reg bus_rst_sync1 = 0;
reg bus_rst_sync2 = 0;
always @(posedge clk_bus) begin
if (arst_n == 0) begin
bus_rst_sync1 <= 0;
bus_rst_sync2 <= 0;
end else begin
...
functional details[stdout] ERROR: not all domains were held in reset during global reset. ERROR: CPU reset did not release after two clk_cpu edges. ERROR: downstream domains released before CPU was safely active. ERROR: BUS reset did not release after the second synchronized stage. ERROR: PERIPH reset did not release after two synchronized stages. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_1 | run_20260427_144342_055801_c17762 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_144342_055801_c17762__sample_1
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync0;
reg cpu_rst_sync1;
always @(posedge clk_cpu) begin
if (arst_n == 0) begin
cpu_rst_sync0 <= 0;
cpu_rst_sync1 <= 0;
end else begin
cpu_rst_sync0 <= cpu_rst_sync1;
cpu_rst_sync1 <= cpu_rst_sync0;
end
end
assign rst_cpu_n = ~(cpu_rst_sync0 | cpu_rst_sync1);
// BUS reset synchronizer
reg bus_rst_sync0;
reg bus_rst_sync1;
always @(posedge clk_bus) begin
if (arst_n == 0 || rst_cpu_n == 0) begin
bus_rst_sync0 <= 0;
bus_rst_sync1 <= 0;
end else begin
...
functional details[stdout] ERROR: not all domains were held in reset during global reset. ERROR: CPU reset released after one edge instead of two. ERROR: downstream domains released before CPU was safely active. ERROR: BUS reset released after one synchronizer stage. ERROR: PERIPH reset released before BUS reset was synchronized. ERROR: PERIPH reset released after one synchronizer stage. ERROR: PERIPH reset did not release after two synchronized stages. ERROR: asynchronous reassertion did not drop all local resets immediately. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | rst_cpu_n is declared here as wire. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// Synchronizers for CPU and BUS domains
reg cpu_sync = 1'b0;
reg bus_sync = 1'b0;
always @(posedge clk_cpu) begin
if (arst_n == 1'b0) begin
rst_cpu_n <= 1'b0;
end else begin
rst_cpu_n <= cpu_sync;
end
end
always @(posedge clk_bus) begin
if (arst_n == 1'b0) begin
rst_bus_n <= 1'b0;
end else begin
rst_bus_n <= bus_sync;
end
end
always @(posedge clk_periph) begin
if (arst_n == 1'b0) begin
...
syntax details[stderr] rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:25: error: rst_bus_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:27: error: rst_bus_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:33: error: rst_periph_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:35: error: rst_periph_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:88: error: Could not find variable ``periph_sync'' in ``triple_reset_sequencer'' /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:90: error: Could not find variable ``periph_sync'' in ``triple_reset_sequencer'' 8 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:17: error: rst_cpu_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:19: error: rst_cpu_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:25: error: rst_bus_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:27: error: rst_bus_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:33: error: rst_periph_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:35: error: rst_periph_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:88: error: Could not find variable ``periph_sync'' in ``tb_task_62.dut'' /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:90: error: Could not find variable ``periph_sync'' in ``tb_task_62.dut'' 8 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": " rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:25: error: rst_bus_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:27: error: rst_bus_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:33: error: rst_periph_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:35: error: rst_periph_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:88: error: Could not find variable ``periph_sync'' in ``triple_reset_sequencer''\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/generated.v:90: error: Could not find variable ``periph_sync'' in ``triple_reset_sequencer''\n8 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:17: error: rst_cpu_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:19: error: rst_cpu_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:25: error: rst_bus_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:27: error: rst_bus_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:33: error: rst_periph_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:35: error: rst_periph_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:88: error: Could not find variable ``periph_sync'' in ``tb_task_62.dut''\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_2/functional/generated.v:90: error: Could not find variable ``periph_sync'' i…
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260427_144342_055801_c17762 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_144342_055801_c17762__sample_2
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync1;
reg cpu_rst_sync2;
always @(posedge clk_cpu) begin
if (arst_n == 0) begin
cpu_rst_sync1 <= 0;
cpu_rst_sync2 <= 0;
end else begin
cpu_rst_sync1 <= cpu_rst_sync2;
cpu_rst_sync2 <= arst_n;
end
end
assign rst_cpu_n = ~(cpu_rst_sync1 | cpu_rst_sync2);
// BUS reset synchronizer
reg bus_rst_sync1;
reg bus_rst_sync2;
always @(posedge clk_bus) begin
if (arst_n == 0) begin
bus_rst_sync1 <= 0;
bus_rst_sync2 <= 0;
end else begin
...
functional details[stdout] ERROR: not all domains were held in reset during global reset. ERROR: CPU reset did not release after two clk_cpu edges. ERROR: downstream domains released before CPU was safely active. ERROR: BUS reset did not release after the second synchronized stage. ERROR: PERIPH reset did not release after two synchronized stages. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | 62/sample_3/generated.v:7: : rst_bus_n is declared here as wire. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// Synchronizers for CPU and BUS domains
reg cpu_sync_0;
reg cpu_sync_1;
reg bus_sync_0;
reg bus_sync_1;
always @(posedge clk_cpu) begin
// Synchronize arst_n to clk_cpu
if (arst_n == 0) begin
cpu_sync_0 <= 1'b0;
end else begin
cpu_sync_0 <= 1'b1;
end
end
always @(posedge clk_bus) begin
// Synchronize arst_n to clk_bus
if (arst_n == 0) begin
bus_sync_0 <= 1'b0;
end else begin
bus_sync_0 <= 1'b1;
end
...
syntax details[stderr] 62/sample_3/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:49: error: rst_bus_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:56: error: rst_periph_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:58: error: rst_periph_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:83: error: rst_periph_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:85: error: rst_periph_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:8: : rst_periph_n is declared here as wire. 8 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:38: error: rst_cpu_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:40: error: rst_cpu_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:47: error: rst_bus_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:49: error: rst_bus_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:56: error: rst_periph_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:58: error: rst_periph_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:83: error: rst_periph_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:85: error: rst_periph_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:8: : rst_periph_n is declared here as wire. 8 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "62/sample_3/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:49: error: rst_bus_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:56: error: rst_periph_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:58: error: rst_periph_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:83: error: rst_periph_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:85: error: rst_periph_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/generated.v:8: : rst_periph_n is declared here as wire.\n8 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:38: error: rst_cpu_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:40: error: rst_cpu_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:47: error: rst_bus_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:49: error: rst_bus_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:56: error: rst_periph_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:58: error: rst_periph_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:83: error: rst_periph_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_3/functional/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eva…
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_144342_055801_c17762 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_144342_055801_c17762__sample_3
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync1;
reg cpu_rst_sync2;
always @(posedge clk_cpu) begin
if (arst_n == 0) begin
cpu_rst_sync1 <= 1'b0;
cpu_rst_sync2 <= 1'b0;
end else begin
cpu_rst_sync1 <= cpu_rst_sync1;
cpu_rst_sync2 <= cpu_rst_sync2;
end
end
assign rst_cpu_n = ~(cpu_rst_sync1 & cpu_rst_sync2);
// BUS reset synchronizer
reg bus_rst_sync1;
reg bus_rst_sync2;
always @(posedge clk_bus) begin
if (arst_n == 0 || rst_cpu_n == 0) begin
bus_rst_sync1 <= 1'b0;
bus_rst_sync2 <= 1'b0;
end else begin
...
functional details[stdout] ERROR: not all domains were held in reset during global reset. ERROR: CPU reset released after one edge instead of two. ERROR: downstream domains released before CPU was safely active. ERROR: BUS reset released after one synchronizer stage. ERROR: PERIPH reset released before BUS reset was synchronized. ERROR: PERIPH reset released after one synchronizer stage. ERROR: PERIPH reset did not release after two synchronized stages. ERROR: asynchronous reassertion did not drop all local resets immediately. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync;
always @(posedge clk_cpu) begin
if (arst_n == 0) begin
cpu_rst_sync <= 1'b0;
end else begin
cpu_rst_sync <= 1'b1;
end
end
// BUS reset synchronizer
reg bus_rst_sync;
always @(posedge clk_bus) begin
if (cpu_rst_sync == 0) begin
bus_rst_sync <= 1'b0;
end else begin
bus_rst_sync <= 1'b1;
end
end
// PERIPH reset synchronizer
reg periph_rst_sync;
...
functional details[stdout] ERROR: not all domains were held in reset during global reset. ERROR: CPU reset did not release after two clk_cpu edges. ERROR: downstream domains released before CPU was safely active. ERROR: BUS reset did not release after the second synchronized stage. ERROR: PERIPH reset did not release after two synchronized stages. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_144342_055801_c17762 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_144342_055801_c17762__sample_4
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync1;
reg cpu_rst_sync2;
always @(posedge clk_cpu) begin
if (arst_n == 0) begin
cpu_rst_sync1 <= 0;
cpu_rst_sync2 <= 0;
end else begin
cpu_rst_sync1 <= cpu_rst_sync2;
cpu_rst_sync2 <= arst_n;
end
end
assign rst_cpu_n = ~(cpu_rst_sync2 | (~arst_n));
// BUS reset synchronizer
reg bus_rst_sync1;
reg bus_rst_sync2;
always @(posedge clk_bus) begin
if (rst_cpu_n == 0) begin
bus_rst_sync1 <= 0;
bus_rst_sync2 <= 0;
end else begin
...
functional details[stdout] ERROR: CPU reset did not release after two clk_cpu edges. ERROR: downstream domains released before CPU was safely active. ERROR: BUS reset released after one synchronizer stage. ERROR: PERIPH reset did not release after two synchronized stages. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_102437_171676_163c0c__sample_5
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync1 = 0;
reg cpu_rst_sync2 = 0;
always @(posedge clk_cpu) begin
if (arst_n == 0) begin
cpu_rst_sync1 <= 0;
cpu_rst_sync2 <= 0;
end else begin
cpu_rst_sync1 <= cpu_rst_sync2;
cpu_rst_sync2 <= arst_n;
end
end
assign rst_cpu_n = ~(cpu_rst_sync2 | (~arst_n));
// BUS reset synchronizer
reg bus_rst_sync1 = 0;
reg bus_rst_sync2 = 0;
always @(posedge clk_bus) begin
if (cpu_rst_sync2 == 0) begin
bus_rst_sync1 <= 0;
bus_rst_sync2 <= 0;
end else begin
...
functional details[stdout] ERROR: CPU reset did not release after two clk_cpu edges. ERROR: downstream domains released before CPU was safely active. ERROR: BUS reset did not release after the second synchronized stage. ERROR: PERIPH reset did not release after two synchronized stages. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | not select part of scalar: periph_rst_sync |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_144342_055801_c17762__sample_5
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync = 1'b0;
always @(posedge clk_cpu) begin
if (arst_n == 1'b0) begin
cpu_rst_sync <= 2'b00;
end else begin
cpu_rst_sync <= {cpu_rst_sync[0], cpu_rst_sync[1]};
end
end
assign rst_cpu_n = ~cpu_rst_sync[1];
// BUS reset synchronizer
reg bus_rst_sync = 1'b0;
always @(posedge clk_bus) begin
if (arst_n == 1'b0 || rst_cpu_n == 1'b0) begin
bus_rst_sync <= 2'b00;
end else begin
bus_rst_sync <= {bus_rst_sync[0], bus_rst_sync[1]};
end
end
assign rst_bus_n = ~bus_rst_sync[1];
...
syntax details[stderr] not select part of scalar: periph_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:42: error: Unable to elaborate r-value: ~(periph_rst_sync['sd1]) /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:17: error: can not select part of scalar: cpu_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:17: error: can not select part of scalar: cpu_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:17: error: Concatenation/replication may not have zero width in this context. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:28: error: can not select part of scalar: bus_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:28: error: can not select part of scalar: bus_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:28: error: Concatenation/replication may not have zero width in this context. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:39: error: can not select part of scalar: periph_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:39: error: can not select part of scalar: periph_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:39: error: Concatenation/replication may not have zero width in this context. 15 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:20: error: can not select part of scalar: cpu_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:20: error: Unable to elaborate r-value: ~(cpu_rst_sync['sd1]) /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:31: error: can not select part of scalar: bus_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:31: error: Unable to elaborate r-value: ~(bus_rst_sync['sd1]) /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:42: error: can not select part of scalar: periph_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:42: error: Unable to elaborate r-value: ~(periph_rst_sync['sd1]) /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:17: error: can not select part of scalar: cpu_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:17: error: can not select part of scalar: cpu_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:17: error: Concatenation/replication may not have zero width in this context. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:28: error: can not select part of scalar: bus_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:28: error: can not select part of scalar: bus_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:28: error: Concatenation/replication may not have zero width in this context. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:39: error: can not select part of scalar: periph_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:39: error: can not select part of scalar: periph_rst_sync /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:39: error: Concatenation/replication may not have zero width in this context. 15 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "not select part of scalar: periph_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:42: error: Unable to elaborate r-value: ~(periph_rst_sync['sd1])\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:17: error: can not select part of scalar: cpu_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:17: error: can not select part of scalar: cpu_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:17: error: Concatenation/replication may not have zero width in this context.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:28: error: can not select part of scalar: bus_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:28: error: can not select part of scalar: bus_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:28: error: Concatenation/replication may not have zero width in this context.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:39: error: can not select part of scalar: periph_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:39: error: can not select part of scalar: periph_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/generated.v:39: error: Concatenation/replication may not have zero width in this context.\n15 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:20: error: can not select part of scalar: cpu_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:20: error: Unable to elaborate r-value: ~(cpu_rst_sync['sd1])\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:31: error: can not select part of scalar: bus_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:31: error: Unable to elaborate r-value: ~(bus_rst_sync['sd1])\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:42: error: can not select part of scalar: periph_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:42: error: Unable to elaborate r-value: ~(periph_rst_sync['sd1])\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:17: error: can not select part of scalar: cpu_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:17: error: can not select part of scalar: cpu_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:17: error: Concatenation/replication may not have zero width in this context.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:28: error: can not select part of scalar: bus_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:28: error: can not select part of scalar: bus_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:28: error: Concatenation/replication may not have zero width in this context.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:39: error: can not select part of scalar: periph_rst_sync\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_5/functional/generated.v:…
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// Synchronizers for CPU and BUS domains
reg cpu_sync_0;
reg cpu_sync_1;
reg bus_sync_0;
reg bus_sync_1;
always @(posedge clk_cpu) begin
// Synchronize arst_n to CPU domain
if (arst_n == 0) begin
cpu_sync_0 <= 0;
end else begin
cpu_sync_0 <= 1;
end
end
always @(posedge clk_cpu) begin
// Synchronize CPU-ready condition to CPU domain
if (cpu_sync_0 == 1) begin
cpu_sync_1 <= 1;
end else begin
cpu_sync_1 <= 0;
end
...
functional details[stdout] ERROR: not all domains were held in reset during global reset. ERROR: CPU reset did not release after two clk_cpu edges. ERROR: downstream domains released before CPU was safely active. ERROR: BUS reset released after one synchronizer stage. ERROR: BUS reset did not release after the second synchronized stage. ERROR: PERIPH reset did not release after two synchronized stages. ERROR: asynchronous reassertion did not drop all local resets immediately. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | ssing__task_62/sample_6/generated.v:6: : rst_cpu_n is declared here as wire. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_144342_055801_c17762__sample_6
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// Synchronizers for CPU and BUS domains
reg sync_cpu_ready;
reg sync_bus_ready;
always @(posedge clk_cpu or negedge arst_n) begin
if (~arst_n) begin
rst_cpu_n <= 0;
sync_cpu_ready <= 0;
end else begin
rst_cpu_n <= ~sync_cpu_ready;
sync_cpu_ready <= ~sync_cpu_ready;
end
end
always @(posedge clk_bus or negedge arst_n) begin
if (~arst_n) begin
rst_bus_n <= 0;
sync_bus_ready <= 0;
end else begin
rst_bus_n <= ~sync_bus_ready;
sync_bus_ready <= ~sync_bus_ready;
end
...
syntax details[stderr] ssing__task_62/sample_6/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:20: error: rst_cpu_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:27: error: rst_bus_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:30: error: rst_bus_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:37: error: rst_periph_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:39: error: rst_periph_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:8: : rst_periph_n is declared here as wire. 6 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:17: error: rst_cpu_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:20: error: rst_cpu_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:27: error: rst_bus_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:30: error: rst_bus_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:37: error: rst_periph_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:39: error: rst_periph_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:8: : rst_periph_n is declared here as wire. 6 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "ssing__task_62/sample_6/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:20: error: rst_cpu_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:27: error: rst_bus_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:30: error: rst_bus_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:37: error: rst_periph_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:39: error: rst_periph_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/generated.v:8: : rst_periph_n is declared here as wire.\n6 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:17: error: rst_cpu_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:20: error: rst_cpu_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:27: error: rst_bus_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:30: error: rst_bus_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:37: error: rst_periph_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:39: error: rst_periph_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_6/functional/generated.v:8: : rst_periph_n is declared here as wire.\n6 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync1 = 0;
reg cpu_rst_sync2 = 0;
always @(posedge clk_cpu) begin
if (arst_n == 0) begin
cpu_rst_sync1 <= 0;
cpu_rst_sync2 <= 0;
end else begin
cpu_rst_sync1 <= cpu_rst_sync2;
cpu_rst_sync2 <= arst_n;
end
end
assign rst_cpu_n = ~cpu_rst_sync2;
// BUS reset synchronizer
reg bus_rst_sync1 = 0;
reg bus_rst_sync2 = 0;
always @(posedge clk_bus) begin
if (arst_n == 0 || rst_cpu_n == 0) begin
bus_rst_sync1 <= 0;
bus_rst_sync2 <= 0;
end else begin
...
functional details[stdout] ERROR: not all domains were held in reset during global reset. ERROR: CPU reset did not release after two clk_cpu edges. ERROR: downstream domains released before CPU was safely active. ERROR: BUS reset released after one synchronizer stage. ERROR: PERIPH reset did not release after two synchronized stages. ERROR: asynchronous reassertion did not drop all local resets immediately. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_144342_055801_c17762 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_144342_055801_c17762__sample_7
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync1;
reg cpu_rst_sync2;
always @(posedge clk_cpu) begin
if (arst_n == 0) begin
cpu_rst_sync1 <= 0;
cpu_rst_sync2 <= 0;
end else begin
cpu_rst_sync1 <= cpu_rst_sync2;
cpu_rst_sync2 <= arst_n;
end
end
assign rst_cpu_n = ~(cpu_rst_sync2 | cpu_rst_sync1);
// BUS reset synchronizer
reg bus_rst_sync1;
reg bus_rst_sync2;
always @(posedge clk_bus) begin
if (arst_n == 0) begin
bus_rst_sync1 <= 0;
bus_rst_sync2 <= 0;
end else begin
...
functional details[stdout] ERROR: not all domains were held in reset during global reset. ERROR: CPU reset did not release after two clk_cpu edges. ERROR: downstream domains released before CPU was safely active. ERROR: BUS reset did not release after the second synchronized stage. ERROR: PERIPH reset did not release after two synchronized stages. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync1;
reg cpu_rst_sync2;
always @(posedge clk_cpu) begin
if (arst_n == 0) begin
cpu_rst_sync1 <= 0;
cpu_rst_sync2 <= 0;
end else begin
cpu_rst_sync1 <= cpu_rst_sync1 || arst_n;
cpu_rst_sync2 <= cpu_rst_sync2 || cpu_rst_sync1;
end
end
assign rst_cpu_n = ~(cpu_rst_sync2 && clk_cpu);
// BUS reset synchronizer
reg bus_rst_sync1;
reg bus_rst_sync2;
always @(posedge clk_bus) begin
if (arst_n == 0 || rst_cpu_n == 0) begin
bus_rst_sync1 <= 0;
bus_rst_sync2 <= 0;
end else begin
...
functional details[stdout] ERROR: not all domains were held in reset during global reset. ERROR: CPU reset released after one edge instead of two. ERROR: CPU reset did not release after two clk_cpu edges. ERROR: downstream domains released before CPU was safely active. ERROR: BUS reset released after one synchronizer stage. ERROR: PERIPH reset released before BUS reset was synchronized. ERROR: PERIPH reset did not release after two synchronized stages. ERROR: asynchronous reassertion did not drop all local resets immediately. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260427_144342_055801_c17762 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_144342_055801_c17762__sample_8
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync1;
reg cpu_rst_sync2;
always @(posedge clk_cpu or negedge arst_n) begin
if (~arst_n) begin
cpu_rst_sync1 <= 0;
cpu_rst_sync2 <= 0;
end else begin
cpu_rst_sync1 <= clk_cpu & ~cpu_rst_sync1;
cpu_rst_sync2 <= cpu_rst_sync1;
end
end
assign rst_cpu_n = ~(cpu_rst_sync2 | arst_n);
// BUS reset synchronizer
reg bus_rst_sync1;
reg bus_rst_sync2;
always @(posedge clk_bus or negedge arst_n) begin
if (~arst_n) begin
bus_rst_sync1 <= 0;
bus_rst_sync2 <= 0;
end else begin
...
functional details[stdout] ERROR: not all domains were held in reset during global reset. ERROR: CPU reset did not release after two clk_cpu edges. ERROR: BUS reset did not release after the second synchronized stage. ERROR: PERIPH reset did not release after two synchronized stages. ERROR: asynchronous reassertion did not drop all local resets immediately. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | _task_62/sample_9/generated.v:7: : rst_bus_n is declared here as wire. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// Synchronizers for CPU and BUS domains
reg sync_cpu_r = 1'b0;
reg sync_cpu_f = 1'b0;
reg sync_bus_r = 1'b0;
reg sync_bus_f = 1'b0;
// Synchronizers for PERIPH domain
reg sync_periph_r = 1'b0;
reg sync_periph_f = 1'b0;
always @(posedge clk_cpu or negedge arst_n) begin
if (!arst_n) begin
rst_cpu_n <= 1'b0;
sync_cpu_r <= 1'b0;
sync_cpu_f <= 1'b0;
end else begin
// Synchronize CPU reset to clk_cpu domain
if (sync_cpu_r) begin
rst_cpu_n <= 1'b0;
sync_cpu_f <= 1'b0;
end else begin
rst_cpu_n <= 1'b1;
...
syntax details[stderr] _task_62/sample_9/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:46: error: rst_bus_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:49: error: rst_bus_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:57: error: rst_periph_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:63: error: rst_periph_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:66: error: rst_periph_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:8: : rst_periph_n is declared here as wire. 9 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:23: error: rst_cpu_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:29: error: rst_cpu_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:32: error: rst_cpu_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:40: error: rst_bus_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:46: error: rst_bus_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:49: error: rst_bus_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:57: error: rst_periph_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:63: error: rst_periph_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:66: error: rst_periph_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:8: : rst_periph_n is declared here as wire. 9 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "_task_62/sample_9/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:46: error: rst_bus_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:49: error: rst_bus_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:57: error: rst_periph_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:63: error: rst_periph_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:66: error: rst_periph_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:8: : rst_periph_n is declared here as wire.\n9 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:23: error: rst_cpu_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:29: error: rst_cpu_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:32: error: rst_cpu_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:40: error: rst_bus_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:46: error: rst_bus_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:49: error: rst_bus_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:57: error: rst_periph_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20…
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | ssing__task_62/sample_9/generated.v:6: : rst_cpu_n is declared here as wire. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_144342_055801_c17762__sample_9
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// Synchronizers for CPU and BUS domains
reg sync_cpu_r = 1'b0;
reg sync_cpu_f = 1'b0;
reg sync_bus_r = 1'b0;
reg sync_bus_f = 1'b0;
// Synchronizers for PERIPH domain
reg sync_periph_r = 1'b0;
reg sync_periph_f = 1'b0;
always @(posedge clk_cpu or negedge arst_n) begin
if (!arst_n) begin
rst_cpu_n <= 1'b0;
sync_cpu_r <= 1'b0;
sync_cpu_f <= 1'b0;
end else begin
// Synchronize CPU reset to clk_cpu domain
if (sync_cpu_r) begin
rst_cpu_n <= ~sync_cpu_f;
end
sync_cpu_r <= 1'b1;
sync_cpu_f <= ~sync_cpu_f;
...
syntax details[stderr] ssing__task_62/sample_9/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:29: error: rst_cpu_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:38: error: rst_bus_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:44: error: rst_bus_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:53: error: rst_periph_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:59: error: rst_periph_n is not a valid l-value in triple_reset_sequencer. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:8: : rst_periph_n is declared here as wire. 6 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:23: error: rst_cpu_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:29: error: rst_cpu_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:6: : rst_cpu_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:38: error: rst_bus_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:44: error: rst_bus_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:7: : rst_bus_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:53: error: rst_periph_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:8: : rst_periph_n is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:59: error: rst_periph_n is not a valid l-value in tb_task_62.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:8: : rst_periph_n is declared here as wire. 6 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "ssing__task_62/sample_9/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:29: error: rst_cpu_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:38: error: rst_bus_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:44: error: rst_bus_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:53: error: rst_periph_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:59: error: rst_periph_n is not a valid l-value in triple_reset_sequencer.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/generated.v:8: : rst_periph_n is declared here as wire.\n6 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:23: error: rst_cpu_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:29: error: rst_cpu_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:6: : rst_cpu_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:38: error: rst_bus_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:44: error: rst_bus_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:7: : rst_bus_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:53: error: rst_periph_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:8: : rst_periph_n is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:59: error: rst_periph_n is not a valid l-value in tb_task_62.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_9/functional/generated.v:8: : rst_periph_n is declared here as wire.\n6 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync1;
reg cpu_rst_sync2;
always @(posedge clk_cpu) begin
if (arst_n == 0) begin
cpu_rst_sync1 <= 0;
cpu_rst_sync2 <= 0;
end else begin
cpu_rst_sync1 <= cpu_rst_sync2;
cpu_rst_sync2 <= cpu_rst_sync1;
end
end
assign rst_cpu_n = ~(cpu_rst_sync1 | cpu_rst_sync2);
// BUS reset synchronizer
reg bus_rst_sync1;
reg bus_rst_sync2;
always @(posedge clk_bus) begin
if (arst_n == 0) begin
bus_rst_sync1 <= 0;
bus_rst_sync2 <= 0;
end else begin
...
functional details[stdout] ERROR: not all domains were held in reset during global reset. ERROR: CPU reset released after one edge instead of two. ERROR: downstream domains released before CPU was safely active. ERROR: BUS reset released after one synchronizer stage. ERROR: PERIPH reset released before BUS reset was synchronized. ERROR: PERIPH reset released after one synchronizer stage. ERROR: PERIPH reset did not release after two synchronized stages. ERROR: asynchronous reassertion did not drop all local resets immediately. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260427_144342_055801_c17762 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260427_144342_055801_c17762__sample_10
generated.v previewmodule triple_reset_sequencer (
input clk_cpu,
input clk_bus,
input clk_periph,
input arst_n,
output rst_cpu_n,
output rst_bus_n,
output rst_periph_n
);
// CPU reset synchronizer
reg cpu_rst_sync1;
reg cpu_rst_sync2;
always @(posedge clk_cpu) begin
if (arst_n == 0) begin
cpu_rst_sync1 <= 0;
cpu_rst_sync2 <= 0;
end else begin
cpu_rst_sync1 <= cpu_rst_sync2;
cpu_rst_sync2 <= cpu_rst_sync1;
end
end
assign rst_cpu_n = ~(cpu_rst_sync1 | cpu_rst_sync2);
// BUS reset synchronizer
reg bus_rst_sync1;
reg bus_rst_sync2;
always @(posedge clk_bus) begin
if (arst_n == 0 || rst_cpu_n == 0) begin
bus_rst_sync1 <= 0;
bus_rst_sync2 <= 0;
end else begin
...
functional details[stdout] ERROR: not all domains were held in reset during global reset. ERROR: CPU reset released after one edge instead of two. ERROR: downstream domains released before CPU was safely active. ERROR: BUS reset released after one synchronizer stage. ERROR: PERIPH reset released before BUS reset was synchronized. ERROR: PERIPH reset released after one synchronizer stage. ERROR: PERIPH reset did not release after two synchronized stages. ERROR: asynchronous reassertion did not drop all local resets immediately. TEST_FAILED /workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|