07_csr_register_map_generation / task_72 | axil_sensor_csr
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_1
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] CTRL; reg [31:0] STATUS; reg [31:0] CMD; ... functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL gain field failed. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: irq_evt did not set irq_sticky. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000000 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: writing 0 incorrectly cleared irq_sticky. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: kick_pulse lasted longer than one cycle. ERROR: AXI-Lite read channel was not ready in idle state. TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_1 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:35: error: 'block_enable' has already been declared in this scope. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_144342_055801_c17762__sample_1
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] ctrl; reg [31:0] status; reg [31:0] cmd; ... syntax details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:35: error: 'block_enable' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:23: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:36: error: 'gain' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:24: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:39: error: 'irq_sticky' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:26: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:40: error: 'hw_level' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:21: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:43: error: 'kick_pulse' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:25: : It was declared here as a net. functional details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:35: error: 'block_enable' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:23: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:36: error: 'gain' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:24: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:39: error: 'irq_sticky' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:26: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:40: error: 'hw_level' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:21: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:43: error: 'kick_pulse' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:25: : It was declared here as a net. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:35: error: 'block_enable' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:23: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:36: error: 'gain' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:24: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:39: error: 'irq_sticky' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:26: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:40: error: 'hw_level' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:21: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:43: error: 'kick_pulse' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/generated.v:25: : It was declared here as a net.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:35: error: 'block_enable' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:23: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:36: error: 'gain' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:24: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:39: error: 'irq_sticky' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:26: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:40: error: 'hw_level' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:21: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:43: error: 'kick_pulse' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_1/functional/generated.v:25: : It was declared here as a net.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:82: syntax error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] ctrl; // CTRL register reg [31:0] status; // STATUS register reg [31:0] cmd; // CMD register ... syntax details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:82: syntax error I give up. functional details[stderr] /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:1: error: timescale directive cannot be inside a module definition. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:263: syntax error I give up. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:82: syntax error\nI give up.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:1: error: timescale directive cannot be inside a module definition.\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:263: syntax error\nI give up.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | map_generation__task_72/sample_2/generated.v:16: : arready is declared here as wire. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_144342_055801_c17762__sample_2
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] CTRL; reg [31:0] STATUS; reg [31:0] CMD; ... syntax details[stderr] map_generation__task_72/sample_2/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:112: error: rvalid is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:19: : rvalid is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:114: error: arready is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:115: error: rvalid is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:19: : rvalid is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:119: error: bresp is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:11: : bresp is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:120: error: rresp is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:18: : rresp is declared here as wire. 25 error(s) during elaboration. functional details[stderr] ta/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:102: error: bvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:12: : bvalid is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:104: error: awready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:6: : awready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:105: error: wready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:10: : wready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:106: error: bvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:12: : bvalid is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:111: error: arready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:112: error: rvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:19: : rvalid is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:114: error: arready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:115: error: rvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:19: : rvalid is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:119: error: bresp is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:11: : bresp is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:120: error: rresp is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:18: : rresp is declared here as wire. 25 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "map_generation__task_72/sample_2/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:112: error: rvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:19: : rvalid is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:114: error: arready is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:115: error: rvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:19: : rvalid is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:119: error: bresp is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:11: : bresp is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:120: error: rresp is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/generated.v:18: : rresp is declared here as wire.\n25 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "ta/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:102: error: bvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:12: : bvalid is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:104: error: awready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:6: : awready is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:105: error: wready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:10: : wready is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:106: error: bvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:12: : bvalid is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:111: error: arready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:112: error: rvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:19: : rvalid is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:114: error: arready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_2/functional/generated.v:16: : arre…
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] CTRL; reg [31:0] STATUS; reg [31:0] CMD; ... functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL gain field failed. ERROR: AXI-Lite read response was not generated correctly. ERROR: irq_evt did not set irq_sticky. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00005c00 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: writing 0 incorrectly cleared irq_sticky. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: kick_pulse did not assert on CMD write. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: CMD register should read as zero. Got 00005c00 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:37: error: block_enable is not a valid l-value in axil_sensor_csr. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_144342_055801_c17762__sample_3
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] ctrl; reg [31:0] status; reg [31:0] cmd; ... syntax details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:37: error: block_enable is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:23: : block_enable is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:39: error: gain is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:24: : gain is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:46: error: irq_sticky is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:26: : irq_sticky is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:48: error: irq_sticky is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:26: : irq_sticky is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:55: error: kick_pulse is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:25: : kick_pulse is declared here as wire. 5 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:37: error: block_enable is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:23: : block_enable is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:39: error: gain is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:24: : gain is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:46: error: irq_sticky is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:26: : irq_sticky is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:48: error: irq_sticky is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:26: : irq_sticky is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:55: error: kick_pulse is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:25: : kick_pulse is declared here as wire. 5 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:37: error: block_enable is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:23: : block_enable is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:39: error: gain is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:24: : gain is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:46: error: irq_sticky is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:26: : irq_sticky is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:48: error: irq_sticky is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:26: : irq_sticky is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:55: error: kick_pulse is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:25: : kick_pulse is declared here as wire.\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:37: error: block_enable is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:23: : block_enable is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:39: error: gain is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:24: : gain is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:46: error: irq_sticky is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:26: : irq_sticky is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:48: error: irq_sticky is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:26: : irq_sticky is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:55: error: kick_pulse is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:25: : kick_pulse is declared here as wire.\n5 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | r_map_generation__task_72/sample_4/generated.v:18: : rresp is declared here as wire. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] ctrl; reg [31:0] status; reg [31:0] cmd; ... syntax details[stderr] r_map_generation__task_72/sample_4/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:117: error: rvalid is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:19: : rvalid is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:119: error: arready is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:120: error: rdata is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:121: error: rresp is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:122: error: rvalid is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:19: : rvalid is declared here as wire. 26 error(s) during elaboration. functional details[stderr] re. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:108: error: bresp is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:11: : bresp is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:109: error: bvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:12: : bvalid is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:114: error: arready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:115: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:116: error: rresp is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:117: error: rvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:19: : rvalid is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:119: error: arready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:120: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:121: error: rresp is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:122: error: rvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:19: : rvalid is declared here as wire. 26 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "r_map_generation__task_72/sample_4/generated.v:18: : rresp is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:117: error: rvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:19: : rvalid is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:119: error: arready is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:120: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:121: error: rresp is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:18: : rresp is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:122: error: rvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:19: : rvalid is declared here as wire.\n26 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "re.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:108: error: bresp is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:11: : bresp is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:109: error: bvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:12: : bvalid is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:114: error: arready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:115: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:116: error: rresp is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:18: : rresp is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:117: error: rvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:19: : rvalid is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:119: error: arready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:16: : arr…
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | map_generation__task_72/sample_4/generated.v:16: : arready is declared here as wire. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_144342_055801_c17762__sample_4
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] ctrl; reg [31:0] status; reg [31:0] cmd; ... syntax details[stderr] map_generation__task_72/sample_4/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:106: error: arready is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:109: error: rdata is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:110: error: rresp is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:111: error: rvalid is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:19: : rvalid is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:113: error: rvalid is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:19: : rvalid is declared here as wire. 21 error(s) during elaboration. functional details[stderr] e. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:95: error: wready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:10: : wready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:98: error: bresp is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:11: : bresp is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:99: error: bvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:12: : bvalid is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:101: error: bvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:12: : bvalid is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:104: error: arready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:106: error: arready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:109: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:110: error: rresp is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:111: error: rvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:19: : rvalid is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:113: error: rvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:19: : rvalid is declared here as wire. 21 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "map_generation__task_72/sample_4/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:106: error: arready is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:109: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:110: error: rresp is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:18: : rresp is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:111: error: rvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:19: : rvalid is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:113: error: rvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:19: : rvalid is declared here as wire.\n21 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "e.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:95: error: wready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:10: : wready is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:98: error: bresp is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:11: : bresp is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:99: error: bvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:12: : bvalid is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:101: error: bvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:12: : bvalid is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:104: error: arready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:106: error: arready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:109: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_4/functional/generated.v:17: : rda…
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:80: error: irq_sticky is not a valid l-value in axil_sensor_csr. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_5
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] ctrl; reg [31:0] status; reg [31:0] cmd; ... syntax details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:80: error: irq_sticky is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:26: : irq_sticky is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:83: error: irq_sticky is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:26: : irq_sticky is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:85: error: irq_sticky is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:26: : irq_sticky is declared here as wire. 3 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:80: error: irq_sticky is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:26: : irq_sticky is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:83: error: irq_sticky is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:26: : irq_sticky is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:85: error: irq_sticky is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:26: : irq_sticky is declared here as wire. 3 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:80: error: irq_sticky is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:26: : irq_sticky is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:83: error: irq_sticky is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:26: : irq_sticky is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:85: error: irq_sticky is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:26: : irq_sticky is declared here as wire.\n3 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:80: error: irq_sticky is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:26: : irq_sticky is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:83: error: irq_sticky is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:26: : irq_sticky is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:85: error: irq_sticky is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:26: : irq_sticky is declared here as wire.\n3 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | r_map_generation__task_72/sample_5/generated.v:18: : rresp is declared here as wire. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_144342_055801_c17762__sample_5
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] ctrl; reg [31:0] status; reg [31:0] cmd; ... syntax details[stderr] r_map_generation__task_72/sample_5/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:119: error: rvalid is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:19: : rvalid is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:121: error: arready is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:122: error: rdata is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:123: error: rresp is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:124: error: rvalid is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:19: : rvalid is declared here as wire. 27 error(s) during elaboration. functional details[stderr] re. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:112: error: bresp is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:11: : bresp is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:113: error: bvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:12: : bvalid is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:116: error: arready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:117: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:118: error: rresp is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:119: error: rvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:19: : rvalid is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:121: error: arready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:122: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:123: error: rresp is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:124: error: rvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:19: : rvalid is declared here as wire. 27 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "r_map_generation__task_72/sample_5/generated.v:18: : rresp is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:119: error: rvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:19: : rvalid is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:121: error: arready is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:122: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:123: error: rresp is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:18: : rresp is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:124: error: rvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:19: : rvalid is declared here as wire.\n27 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "re.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:112: error: bresp is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:11: : bresp is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:113: error: bvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:12: : bvalid is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:116: error: arready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:117: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:118: error: rresp is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:18: : rresp is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:119: error: rvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:19: : rvalid is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:121: error: arready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:16: : arr…
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | ister_map_generation__task_72/sample_6/generated.v:17: : rdata is declared here as wire. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [15:0] ctrl; // CTRL register reg [15:0] status; // STATUS register reg [15:0] cmd; // CMD register ... syntax details[stderr] ister_map_generation__task_72/sample_6/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:113: error: rresp is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:114: error: rvalid is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:19: : rvalid is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:116: error: rdata is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:117: error: rresp is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:118: error: rvalid is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:19: : rvalid is declared here as wire. 24 error(s) during elaboration. functional details[stderr] as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:102: error: bvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:12: : bvalid is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:106: error: arready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:108: error: arready is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:16: : arready is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:112: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:113: error: rresp is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:114: error: rvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:19: : rvalid is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:116: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:117: error: rresp is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:18: : rresp is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:118: error: rvalid is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:19: : rvalid is declared here as wire. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:40: warning: output port awready is coerced to inout. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:44: warning: output port wready is coerced to inout. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:50: warning: output port arready is coerced to inout. 24 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "ister_map_generation__task_72/sample_6/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:113: error: rresp is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:18: : rresp is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:114: error: rvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:19: : rvalid is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:116: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:117: error: rresp is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:18: : rresp is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:118: error: rvalid is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:19: : rvalid is declared here as wire.\n24 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": " as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:102: error: bvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:12: : bvalid is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:106: error: arready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:108: error: arready is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:16: : arready is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:112: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:113: error: rresp is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:18: : rresp is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:114: error: rvalid is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:19: : rvalid is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:116: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:17:…
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:6: : It was declared here as a net. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_144342_055801_c17762__sample_6
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] CTRL; reg [31:0] STATUS; reg [31:0] CMD; ... syntax details[stderr] tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:6: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:36: error: 'wready' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:10: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:37: error: 'bvalid' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:12: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:38: error: 'rvalid' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:19: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:39: error: 'kick_pulse' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:25: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:40: error: 'irq_sticky' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:26: : It was declared here as a net. functional details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:35: error: 'awready' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:6: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:36: error: 'wready' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:10: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:37: error: 'bvalid' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:12: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:38: error: 'rvalid' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:19: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:39: error: 'kick_pulse' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:25: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:40: error: 'irq_sticky' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:26: : It was declared here as a net. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:6: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:36: error: 'wready' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:10: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:37: error: 'bvalid' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:12: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:38: error: 'rvalid' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:19: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:39: error: 'kick_pulse' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:25: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:40: error: 'irq_sticky' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:26: : It was declared here as a net.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:35: error: 'awready' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:6: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:36: error: 'wready' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:10: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:37: error: 'bvalid' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:12: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:38: error: 'rvalid' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:19: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:39: error: 'kick_pulse' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:25: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:40: error: 'irq_sticky' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:26: : It was declared here as a net.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:120: syntax error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Register map reg [31:0] CTRL; reg [31:0] STATUS; reg [31:0] CMD; ... syntax details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:120: syntax error I give up. functional details[stderr] /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:1: error: timescale directive cannot be inside a module definition. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:263: syntax error I give up. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:120: syntax error\nI give up.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:1: error: timescale directive cannot be inside a module definition.\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:263: syntax error\nI give up.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_144342_055801_c17762 | failed | failed | failed | skipped | failed | extract | Model response is empty |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_144342_055801_c17762__sample_7
synthesis details[error] None errors[][
{
"stage": "model_request",
"code": "model_request.failed",
"message": "HTTPConnectionPool(host='ollama', port=11434): Read timed out. (read timeout=120)",
"retryable": true,
"details": {}
},
{
"stage": "extract",
"code": "extract.no_verilog_found",
"message": "Model response is empty",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": false,
"extract_ok": false,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | s wire. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] ctrl; // CTRL register reg [31:0] status; // STATUS register reg [31:0] cmd; // CMD register ... syntax details[stderr] s wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:138: error: kick_pulse_int is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:40: : kick_pulse_int is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:140: error: kick_pulse_int is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:40: : kick_pulse_int is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:148: error: irq_sticky_int is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:41: : irq_sticky_int is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:151: error: irq_sticky_int is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:41: : irq_sticky_int is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:153: error: irq_sticky_int is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:41: : irq_sticky_int is declared here as wire. 21 error(s) during elaboration. functional details[stderr] l/generated.v:114: error: arready_int is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:38: : arready_int is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:122: error: rvalid_int is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:39: : rvalid_int is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:125: error: rvalid_int is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:39: : rvalid_int is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:127: error: rvalid_int is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:39: : rvalid_int is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:135: error: kick_pulse_int is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:40: : kick_pulse_int is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:138: error: kick_pulse_int is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:40: : kick_pulse_int is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:140: error: kick_pulse_int is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:40: : kick_pulse_int is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:148: error: irq_sticky_int is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:41: : irq_sticky_int is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:151: error: irq_sticky_int is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:41: : irq_sticky_int is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:153: error: irq_sticky_int is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:41: : irq_sticky_int is declared here as wire. 21 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "s wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:138: error: kick_pulse_int is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:40: : kick_pulse_int is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:140: error: kick_pulse_int is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:40: : kick_pulse_int is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:148: error: irq_sticky_int is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:41: : irq_sticky_int is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:151: error: irq_sticky_int is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:41: : irq_sticky_int is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:153: error: irq_sticky_int is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:41: : irq_sticky_int is declared here as wire.\n21 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "l/generated.v:114: error: arready_int is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:38: : arready_int is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:122: error: rvalid_int is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:39: : rvalid_int is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:125: error: rvalid_int is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:39: : rvalid_int is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:127: error: rvalid_int is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:39: : rvalid_int is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:135: error: kick_pulse_int is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:40: : kick_pulse_int is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:138: error: kick_pulse_int is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:40: : kick_pulse_int is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:140: error: kick_pulse_int is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:40: : kick_pulse_int is declared here as wire.\n/data/eval/out/run_20…
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260427_144342_055801_c17762 | failed | failed | failed | skipped | failed | extract | Model response is empty |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_144342_055801_c17762__sample_8
synthesis details[error] None errors[][
{
"stage": "model_request",
"code": "model_request.failed",
"message": "HTTPConnectionPool(host='ollama', port=11434): Read timed out. (read timeout=120)",
"retryable": true,
"details": {}
},
{
"stage": "extract",
"code": "extract.no_verilog_found",
"message": "Model response is empty",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": false,
"extract_ok": false,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | 63c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:35: error: 'block_enable' has already been declared in this scope. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] ctrl; reg [31:0] status; reg [31:0] cmd; ... syntax details[stderr] 63c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:35: error: 'block_enable' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:23: : It was declared here as a net. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:36: error: 'gain' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:24: : It was declared here as a net. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:39: error: 'irq_sticky' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:26: : It was declared here as a net. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:40: error: 'hw_level' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:21: : It was declared here as a net. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:43: error: 'kick_pulse' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:25: : It was declared here as a net. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:106: syntax error I give up. functional details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:35: error: 'block_enable' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:23: : It was declared here as a net. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:36: error: 'gain' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:24: : It was declared here as a net. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:39: error: 'irq_sticky' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:26: : It was declared here as a net. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:40: error: 'hw_level' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:21: : It was declared here as a net. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:43: error: 'kick_pulse' has already been declared in this scope. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:25: : It was declared here as a net. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:1: error: timescale directive cannot be inside a module definition. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:263: syntax error I give up. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "63c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:35: error: 'block_enable' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:23: : It was declared here as a net.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:36: error: 'gain' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:24: : It was declared here as a net.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:39: error: 'irq_sticky' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:26: : It was declared here as a net.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:40: error: 'hw_level' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:21: : It was declared here as a net.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:43: error: 'kick_pulse' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:25: : It was declared here as a net.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:106: syntax error\nI give up.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:35: error: 'block_enable' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:23: : It was declared here as a net.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:36: error: 'gain' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:24: : It was declared here as a net.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:39: error: 'irq_sticky' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:26: : It was declared here as a net.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:40: error: 'hw_level' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:21: : It was declared here as a net.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:43: error: 'kick_pulse' has already been declared in this scope.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:25: : It was declared here as a net.\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:1: error: timescale directive cannot be inside a module definition.\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:263: syntax error\nI give up.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:69: error: rdata is not a valid l-value in axil_sensor_csr. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_144342_055801_c17762__sample_9
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] CTRL; reg [31:0] STATUS; reg [31:0] CMD; ... syntax details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:69: error: rdata is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:70: error: rdata is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:71: error: rdata is not a valid l-value in axil_sensor_csr. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:17: : rdata is declared here as wire. 3 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:69: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:70: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:17: : rdata is declared here as wire. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:71: error: rdata is not a valid l-value in tb_task_72.dut. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:17: : rdata is declared here as wire. 3 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:69: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:70: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:71: error: rdata is not a valid l-value in axil_sensor_csr.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:17: : rdata is declared here as wire.\n3 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:69: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:70: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:17: : rdata is declared here as wire.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:71: error: rdata is not a valid l-value in tb_task_72.dut.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:17: : rdata is declared here as wire.\n3 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] ctrl; reg [31:0] status; reg [31:0] cmd; ... functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL gain field failed. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read without IRQ bit set returned wrong value. Got zzzzzzzz ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read with IRQ bit set returned wrong value. Got zzzzzzzz ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: AXI-Lite CMD write response was not generated correctly. ERROR: kick_pulse lasted longer than one cycle. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: CMD register should read as zero. Got zzzzzzzz TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260427_144342_055801_c17762 | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:35: error: 'awready' has already been declared in this scope. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_144342_055801_c17762__sample_10
generated.v previewmodule axil_sensor_csr ( input clk, input rst_n, input [7:0] awaddr, input awvalid, output awready, input [31:0] wdata, input [3:0] wstrb, input wvalid, output wready, output [1:0] bresp, output bvalid, input bready, input [7:0] araddr, input arvalid, output arready, output [31:0] rdata, output [1:0] rresp, output rvalid, input rready, input [7:0] hw_level, input irq_evt, output block_enable, output [7:0] gain, output kick_pulse, output irq_sticky ); // Registers reg [31:0] CTRL; reg [31:0] STATUS; reg [31:0] CMD; ... syntax details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:35: error: 'awready' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:6: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:36: error: 'wready' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:10: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:37: error: 'bvalid' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:12: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:38: error: 'arready' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:16: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:39: error: 'rvalid' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:19: : It was declared here as a net. functional details[stderr] /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:35: error: 'awready' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:6: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:36: error: 'wready' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:10: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:37: error: 'bvalid' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:12: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:38: error: 'arready' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:16: : It was declared here as a net. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:39: error: 'rvalid' has already been declared in this scope. /data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:19: : It was declared here as a net. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:35: error: 'awready' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:6: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:36: error: 'wready' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:10: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:37: error: 'bvalid' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:12: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:38: error: 'arready' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:16: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:39: error: 'rvalid' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:19: : It was declared here as a net.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:35: error: 'awready' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:6: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:36: error: 'wready' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:10: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:37: error: 'bvalid' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:12: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:38: error: 'arready' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:16: : It was declared here as a net.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:39: error: 'rvalid' has already been declared in this scope.\n/data/eval/out/run_20260427_144342_055801_c17762/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:19: : It was declared here as a net.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|