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codellama:13b | RAG on

03_low_power_design / task_34 | soc_top

benchmarkilyasov
task_idilyasov/03_low_power_design/task_34
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260426_075435_225972_f32200

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_075435_225972_f32200 ok failed failed skipped failed syntax /data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_1/generated.v:12: error: Unknown module type: aon_ctrl
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260426_075435_225972_f32200__sample_1
generated.v preview 
module soc_top (
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output [31:0] data_out,
    output pwr_enable,
    output iso_en
);

    // Submodules
    aon_ctrl aon_ctrl (
        .clk(clk),
        .rst_n(rst_n),
        .sleep_req(sleep_req),
        .pwr_enable(pwr_enable),
        .iso_en(iso_en)
    );

    pd_dsp pd_dsp (
        .clk(clk),
        .rst_n(rst_n),
        .sleep_req(sleep_req),
        .data_in(data_in),
        .data_out(data_out)
    );

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_1/generated.v:12: error: Unknown module type: aon_ctrl
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_1/generated.v:20: error: Unknown module type: pd_dsp
3 error(s) during elaboration.
*** These modules were missing:
        aon_ctrl referenced 1 times.
        pd_dsp referenced 1 times.
***
functional details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: error: Unknown module type: aon_ctrl
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:20: error: Unknown module type: pd_dsp
3 error(s) during elaboration.
*** These modules were missing:
        aon_ctrl referenced 1 times.
        pd_dsp referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_1/generated.v:12: error: Unknown module type: aon_ctrl\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_1/generated.v:20: error: Unknown module type: pd_dsp\n3 error(s) during elaboration.\n*** These modules were missing:\n        aon_ctrl referenced 1 times.\n        pd_dsp referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:12: error: Unknown module type: aon_ctrl\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_1/functional/generated.v:20: error: Unknown module type: pd_dsp\n3 error(s) during elaboration.\n*** These modules were missing:\n        aon_ctrl referenced 1 times.\n        pd_dsp referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_075435_225972_f32200 ok failed failed skipped failed syntax /data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_2/generated.v:12: error: Unknown module type: aon_ctrl
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260426_075435_225972_f32200__sample_2
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output [31:0] data_out,
    output pwr_enable,
    output iso_en
);

// Instantiate submodules
aon_ctrl aon_ctrl_inst (
    .clk(clk),
    .rst_n(rst_n),
    .sleep_req(sleep_req),
    .pwr_enable(pwr_enable),
    .iso_en(iso_en)
);

pd_dsp pd_dsp_inst (
    .clk(clk),
    .rst_n(rst_n),
    .data_in(data_in),
    .data_out(data_out)
);

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_2/generated.v:12: error: Unknown module type: aon_ctrl
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_2/generated.v:20: error: Unknown module type: pd_dsp
3 error(s) during elaboration.
*** These modules were missing:
        aon_ctrl referenced 1 times.
        pd_dsp referenced 1 times.
***
functional details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: error: Unknown module type: aon_ctrl
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:20: error: Unknown module type: pd_dsp
3 error(s) during elaboration.
*** These modules were missing:
        aon_ctrl referenced 1 times.
        pd_dsp referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_2/generated.v:12: error: Unknown module type: aon_ctrl\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_2/generated.v:20: error: Unknown module type: pd_dsp\n3 error(s) during elaboration.\n*** These modules were missing:\n        aon_ctrl referenced 1 times.\n        pd_dsp referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:12: error: Unknown module type: aon_ctrl\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_2/functional/generated.v:20: error: Unknown module type: pd_dsp\n3 error(s) during elaboration.\n*** These modules were missing:\n        aon_ctrl referenced 1 times.\n        pd_dsp referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_075435_225972_f32200 ok failed failed skipped failed syntax /data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/generated.v:38: error: 'pwr_enable' has already been declared in this scope.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260426_075435_225972_f32200__sample_3
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output [31:0] data_out,
    output pwr_enable,
    output iso_en
);

    // Submodules
    aon_ctrl aon_ctrl_inst (
        .clk(clk),
        .rst_n(rst_n),
        .sleep_req(sleep_req),
        .pwr_enable(pwr_enable),
        .iso_en(iso_en)
    );

    pd_dsp pd_dsp_inst (
        .clk(clk),
        .rst_n(rst_n),
        .data_in(data_in),
        .data_out(data_out)
    );

endmodule

module aon_ctrl(
    input clk,
    input rst_n,
    input sleep_req,
...
syntax details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/generated.v:38: error: 'pwr_enable' has already been declared in this scope.
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/generated.v:33:      : It was declared here as a net.
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/generated.v:39: error: 'iso_en' has already been declared in this scope.
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/generated.v:34:      : It was declared here as a net.
functional details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:38: error: 'pwr_enable' has already been declared in this scope.
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:33:      : It was declared here as a net.
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:39: error: 'iso_en' has already been declared in this scope.
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:34:      : It was declared here as a net.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/generated.v:38: error: 'pwr_enable' has already been declared in this scope.\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/generated.v:33:      : It was declared here as a net.\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/generated.v:39: error: 'iso_en' has already been declared in this scope.\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/generated.v:34:      : It was declared here as a net.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:38: error: 'pwr_enable' has already been declared in this scope.\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:33:      : It was declared here as a net.\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:39: error: 'iso_en' has already been declared in this scope.\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_3/functional/generated.v:34:      : It was declared here as a net.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_075435_225972_f32200 failed failed failed skipped failed extract No module/endmodule block found in model response
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260426_075435_225972_f32200__sample_4
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "extract",
    "code": "extract.no_verilog_found",
    "message": "No module/endmodule block found in model response",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": false,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_075435_225972_f32200 ok failed failed skipped failed syntax /data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_5/generated.v:12: error: Unknown module type: aon_ctrl
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260426_075435_225972_f32200__sample_5
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output [31:0] data_out,
    output pwr_enable,
    output iso_en
);

// Instantiate submodules
aon_ctrl aon_ctrl_inst (
    .clk(clk),
    .rst_n(rst_n),
    .sleep_req(sleep_req),
    .pwr_enable(pwr_enable),
    .iso_en(iso_en)
);

pd_dsp pd_dsp_inst (
    .clk(clk),
    .rst_n(rst_n),
    .data_in(data_in),
    .data_out(data_out)
);

// Connect submodules
assign aon_ctrl_inst.sleep_req = sleep_req;
assign pd_dsp_inst.clk = clk;
assign pd_dsp_inst.rst_n = rst_n;
assign pd_dsp_inst.data_in = data_in;
assign pd_dsp_inst.data_out = data_out;
...
syntax details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_5/generated.v:12: error: Unknown module type: aon_ctrl
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_5/generated.v:20: error: Unknown module type: pd_dsp
3 error(s) during elaboration.
*** These modules were missing:
        aon_ctrl referenced 1 times.
        pd_dsp referenced 1 times.
***
functional details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:12: error: Unknown module type: aon_ctrl
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:20: error: Unknown module type: pd_dsp
3 error(s) during elaboration.
*** These modules were missing:
        aon_ctrl referenced 1 times.
        pd_dsp referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_5/generated.v:12: error: Unknown module type: aon_ctrl\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_5/generated.v:20: error: Unknown module type: pd_dsp\n3 error(s) during elaboration.\n*** These modules were missing:\n        aon_ctrl referenced 1 times.\n        pd_dsp referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:12: error: Unknown module type: aon_ctrl\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_5/functional/generated.v:20: error: Unknown module type: pd_dsp\n3 error(s) during elaboration.\n*** These modules were missing:\n        aon_ctrl referenced 1 times.\n        pd_dsp referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_075435_225972_f32200 failed failed failed skipped failed extract No module/endmodule block found in model response
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260426_075435_225972_f32200__sample_6
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "extract",
    "code": "extract.no_verilog_found",
    "message": "No module/endmodule block found in model response",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": false,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_075435_225972_f32200 ok failed failed skipped failed syntax /data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: error: Unknown module type: aon_ctrl
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260426_075435_225972_f32200__sample_7
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output [31:0] data_out,
    output pwr_enable,
    output iso_en
);

// Instantiate submodules
aon_ctrl aon(clk, rst_n, sleep_req, data_in, data_out, pwr_enable, iso_en);
pd_dsp pd(clk, rst_n, sleep_req, data_in, data_out, pwr_enable, iso_en);

// Connect submodules
assign aon.sleep_req = sleep_req;
assign aon.data_in = data_in;
assign pd.data_in = data_in;
assign data_out = aon.data_out | pd.data_out;
assign pwr_enable = aon.pwr_enable & pd.pwr_enable;
assign iso_en = aon.iso_en | pd.iso_en;

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: error: Unknown module type: aon_ctrl
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_7/generated.v:13: error: Unknown module type: pd_dsp
3 error(s) during elaboration.
*** These modules were missing:
        aon_ctrl referenced 1 times.
        pd_dsp referenced 1 times.
***
functional details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: error: Unknown module type: aon_ctrl
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:13: error: Unknown module type: pd_dsp
3 error(s) during elaboration.
*** These modules were missing:
        aon_ctrl referenced 1 times.
        pd_dsp referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_7/generated.v:12: error: Unknown module type: aon_ctrl\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_7/generated.v:13: error: Unknown module type: pd_dsp\n3 error(s) during elaboration.\n*** These modules were missing:\n        aon_ctrl referenced 1 times.\n        pd_dsp referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:12: error: Unknown module type: aon_ctrl\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_7/functional/generated.v:13: error: Unknown module type: pd_dsp\n3 error(s) during elaboration.\n*** These modules were missing:\n        aon_ctrl referenced 1 times.\n        pd_dsp referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_075435_225972_f32200 failed failed failed skipped failed extract No module/endmodule block found in model response
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260426_075435_225972_f32200__sample_8
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "extract",
    "code": "extract.no_verilog_found",
    "message": "No module/endmodule block found in model response",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": false,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_075435_225972_f32200 ok failed failed skipped failed syntax /data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: error: Unknown module type: aon_ctrl
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260426_075435_225972_f32200__sample_9
generated.v preview 
module soc_top(
    input clk,
    input rst_n,
    input sleep_req,
    input [31:0] data_in,
    output [31:0] data_out,
    output pwr_enable,
    output iso_en
);

// Instantiate submodules
aon_ctrl aon_ctrl_inst(
    .clk(clk),
    .rst_n(rst_n),
    .sleep_req(sleep_req),
    .pwr_enable(pwr_enable),
    .iso_en(iso_en)
);

pd_dsp pd_dsp_inst(
    .clk(clk),
    .rst_n(rst_n),
    .data_in(data_in),
    .data_out(data_out)
);

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: error: Unknown module type: aon_ctrl
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_9/generated.v:20: error: Unknown module type: pd_dsp
3 error(s) during elaboration.
*** These modules were missing:
        aon_ctrl referenced 1 times.
        pd_dsp referenced 1 times.
***
functional details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: error: Unknown module type: aon_ctrl
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:20: error: Unknown module type: pd_dsp
3 error(s) during elaboration.
*** These modules were missing:
        aon_ctrl referenced 1 times.
        pd_dsp referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_9/generated.v:12: error: Unknown module type: aon_ctrl\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_9/generated.v:20: error: Unknown module type: pd_dsp\n3 error(s) during elaboration.\n*** These modules were missing:\n        aon_ctrl referenced 1 times.\n        pd_dsp referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:12: error: Unknown module type: aon_ctrl\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__03_low_power_design__task_34/sample_9/functional/generated.v:20: error: Unknown module type: pd_dsp\n3 error(s) during elaboration.\n*** These modules were missing:\n        aon_ctrl referenced 1 times.\n        pd_dsp referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_075435_225972_f32200 failed failed failed skipped failed extract No module/endmodule block found in model response
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__03_low_power_design__task_34\samples\run_20260426_075435_225972_f32200__sample_10
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "extract",
    "code": "extract.no_verilog_found",
    "message": "No module/endmodule block found in model response",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": false,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}