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codellama:13b | RAG on

06_reset_domain_crossing / task_62 | triple_reset_sequencer

benchmarkilyasov
task_idilyasov/06_reset_domain_crossing/task_62
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260426_075435_225972_f32200

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_075435_225972_f32200 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_075435_225972_f32200__sample_1
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

// Synchronize the CPU reset to the CPU clock domain
reg cpu_rst_sync;
always @(posedge clk_cpu or negedge arst_n) begin
    if (~arst_n) begin
        cpu_rst_sync <= 1'b0;
    end else begin
        cpu_rst_sync <= 1'b1;
    end
end

// Synchronize the BUS reset to the BUS clock domain
reg bus_rst_sync;
always @(posedge clk_bus or negedge arst_n) begin
    if (~arst_n) begin
        bus_rst_sync <= 1'b0;
    end else begin
        bus_rst_sync <= 1'b1;
    end
end

// Synchronize the PERIPH reset to the PERIPH clock domain
reg periph_rst_sync;
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset did not release after two synchronized stages.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_075435_225972_f32200 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_075435_225972_f32200__sample_2
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

// Synchronize the CPU reset to the CPU clock domain
reg cpu_rst_sync;
always @(posedge clk_cpu or negedge arst_n) begin
    if (~arst_n) begin
        cpu_rst_sync <= 1'b0;
    end else begin
        cpu_rst_sync <= 1'b1;
    end
end

// Synchronize the BUS reset to the BUS clock domain
reg bus_rst_sync;
always @(posedge clk_bus or negedge arst_n) begin
    if (~arst_n) begin
        bus_rst_sync <= 1'b0;
    end else begin
        bus_rst_sync <= 1'b1;
    end
end

// Synchronize the PERIPH reset to the PERIPH clock domain
reg periph_rst_sync;
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset did not release after two synchronized stages.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_075435_225972_f32200 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: BUS reset released after one synchronizer stage.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_075435_225972_f32200__sample_3
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

// Synchronizer for CPU reset
reg [1:0] cpu_rst_sync = 2'b11;
always @(posedge clk_cpu or negedge arst_n) begin
    if (~arst_n) begin
        cpu_rst_sync <= 2'b11;
    end else begin
        cpu_rst_sync <= {cpu_rst_sync[0], 1'b0};
    end
end
assign rst_cpu_n = ~cpu_rst_sync[1];

// Synchronizer for BUS reset
reg [1:0] bus_rst_sync = 2'b11;
always @(posedge clk_bus or negedge arst_n) begin
    if (~arst_n) begin
        bus_rst_sync <= 2'b11;
    end else begin
        bus_rst_sync <= {bus_rst_sync[0], 1'b0};
    end
end
assign rst_bus_n = ~bus_rst_sync[1];
...
functional details 
[stdout]
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: BUS reset released after one synchronizer stage.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_075435_225972_f32200 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: BUS reset released after one synchronizer stage.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_075435_225972_f32200__sample_4
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

// CPU reset synchronizer
reg [1:0] cpu_rst_sync = 2'b11;
always @(posedge clk_cpu or negedge arst_n) begin
    if (!arst_n) begin
        cpu_rst_sync <= 2'b11;
    end else begin
        cpu_rst_sync <= {cpu_rst_sync[0], 1'b0};
    end
end
assign rst_cpu_n = ~cpu_rst_sync[1];

// BUS reset synchronizer
reg [1:0] bus_rst_sync = 2'b11;
always @(posedge clk_bus or negedge arst_n) begin
    if (!arst_n) begin
        bus_rst_sync <= 2'b11;
    end else begin
        bus_rst_sync <= {bus_rst_sync[0], 1'b0};
    end
end
assign rst_bus_n = ~bus_rst_sync[1];
...
functional details 
[stdout]
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: BUS reset released after one synchronizer stage.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_075435_225972_f32200 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_075435_225972_f32200__sample_5
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

// Synchronize the CPU reset to the CPU clock domain
reg cpu_rst_sync;
always @(posedge clk_cpu or negedge arst_n) begin
    if (~arst_n) begin
        cpu_rst_sync <= 1'b0;
    end else begin
        cpu_rst_sync <= 1'b1;
    end
end

// Synchronize the BUS reset to the BUS clock domain
reg bus_rst_sync;
always @(posedge clk_bus or negedge arst_n) begin
    if (~arst_n) begin
        bus_rst_sync <= 1'b0;
    end else begin
        bus_rst_sync <= 1'b1;
    end
end

// Synchronize the PERIPH reset to the PERIPH clock domain
reg periph_rst_sync;
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_075435_225972_f32200 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: BUS reset released after one synchronizer stage.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_075435_225972_f32200__sample_6
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

// CPU reset synchronizer
reg [1:0] cpu_rst_sync = 2'b11;
always @(posedge clk_cpu or negedge arst_n) begin
    if (~arst_n) begin
        cpu_rst_sync <= 2'b11;
    end else begin
        cpu_rst_sync <= {cpu_rst_sync[0], 1'b0};
    end
end
assign rst_cpu_n = ~cpu_rst_sync[1];

// BUS reset synchronizer
reg [1:0] bus_rst_sync = 2'b11;
always @(posedge clk_bus or negedge arst_n) begin
    if (~arst_n) begin
        bus_rst_sync <= 2'b11;
    end else begin
        bus_rst_sync <= {bus_rst_sync[0], 1'b0};
    end
end
assign rst_bus_n = ~bus_rst_sync[1];
...
functional details 
[stdout]
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: BUS reset released after one synchronizer stage.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_075435_225972_f32200 ok failed failed skipped failed syntax /data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/generated.v:42: error: can not select part of scalar: cpu_rst
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_075435_225972_f32200__sample_7
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

// CPU reset synchronizer
reg cpu_rst = 1'b0;
always @(posedge clk_cpu or negedge arst_n) begin
    if (~arst_n) begin
        cpu_rst <= 1'b0;
    end else begin
        cpu_rst <= 2'b11;
    end
end

// BUS reset synchronizer
reg bus_rst = 1'b0;
always @(posedge clk_bus or negedge arst_n) begin
    if (~arst_n) begin
        bus_rst <= 1'b0;
    end else begin
        bus_rst <= 2'b11;
    end
end

// PERIPH reset synchronizer
reg periph_rst = 1'b0;
...
syntax details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/generated.v:42: error: can not select part of scalar: cpu_rst
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/generated.v:42: error: Unable to elaborate r-value: cpu_rst['sd1]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/generated.v:43: error: can not select part of scalar: bus_rst
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/generated.v:43: error: Unable to elaborate r-value: bus_rst['sd1]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/generated.v:44: error: can not select part of scalar: periph_rst
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/generated.v:44: error: Unable to elaborate r-value: periph_rst['sd1]
6 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/functional/generated.v:42: error: can not select part of scalar: cpu_rst
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/functional/generated.v:42: error: Unable to elaborate r-value: cpu_rst['sd1]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/functional/generated.v:43: error: can not select part of scalar: bus_rst
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/functional/generated.v:43: error: Unable to elaborate r-value: bus_rst['sd1]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/functional/generated.v:44: error: can not select part of scalar: periph_rst
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/functional/generated.v:44: error: Unable to elaborate r-value: periph_rst['sd1]
6 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/generated.v:42: error: can not select part of scalar: cpu_rst\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/generated.v:42: error: Unable to elaborate r-value: cpu_rst['sd1]\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/generated.v:43: error: can not select part of scalar: bus_rst\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/generated.v:43: error: Unable to elaborate r-value: bus_rst['sd1]\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/generated.v:44: error: can not select part of scalar: periph_rst\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/generated.v:44: error: Unable to elaborate r-value: periph_rst['sd1]\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/functional/generated.v:42: error: can not select part of scalar: cpu_rst\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/functional/generated.v:42: error: Unable to elaborate r-value: cpu_rst['sd1]\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/functional/generated.v:43: error: can not select part of scalar: bus_rst\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/functional/generated.v:43: error: Unable to elaborate r-value: bus_rst['sd1]\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/functional/generated.v:44: error: can not select part of scalar: periph_rst\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__06_reset_domain_crossing__task_62/sample_7/functional/generated.v:44: error: Unable to elaborate r-value: periph_rst['sd1]\n6 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_075435_225972_f32200 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_075435_225972_f32200__sample_8
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

// Synchronize the CPU reset to the CPU clock domain
reg cpu_rst_sync;
always @(posedge clk_cpu or negedge arst_n) begin
    if (~arst_n) begin
        cpu_rst_sync <= 1'b0;
    end else begin
        cpu_rst_sync <= 1'b1;
    end
end

// Synchronize the BUS reset to the BUS clock domain
reg bus_rst_sync;
always @(posedge clk_bus or negedge arst_n) begin
    if (~arst_n) begin
        bus_rst_sync <= 1'b0;
    end else begin
        bus_rst_sync <= 1'b1;
    end
end

// Synchronize the PERIPH reset to the PERIPH clock domain
reg periph_rst_sync;
...
functional details 
[stdout]
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_075435_225972_f32200 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_075435_225972_f32200__sample_9
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

// Synchronize the CPU reset to the CPU clock domain
reg cpu_rst_sync;
always @(posedge clk_cpu) begin
    if (arst_n == 0) begin
        cpu_rst_sync <= 1'b0;
    end else begin
        cpu_rst_sync <= 1'b1;
    end
end

// Synchronize the BUS reset to the BUS clock domain
reg bus_rst_sync;
always @(posedge clk_bus) begin
    if (cpu_rst_sync == 0) begin
        bus_rst_sync <= 1'b0;
    end else begin
        bus_rst_sync <= 1'b1;
    end
end

// Synchronize the PERIPH reset to the PERIPH clock domain
reg periph_rst_sync;
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_075435_225972_f32200 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_075435_225972_f32200__sample_10
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

// CPU reset synchronizer
reg cpu_rst = 1'b0;
always @(posedge clk_cpu) begin
    if (arst_n == 0) begin
        cpu_rst <= 1'b0;
    end else begin
        cpu_rst <= 1'b1;
    end
end

// BUS reset synchronizer
reg bus_rst = 1'b0;
always @(posedge clk_bus) begin
    if (cpu_rst == 1'b0) begin
        bus_rst <= 1'b0;
    end else begin
        bus_rst <= 1'b1;
    end
end

// PERIPH reset synchronizer
reg periph_rst = 1'b0;
...
functional details 
[stdout]
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset released after one edge instead of two.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}