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codellama:13b | RAG on

07_csr_register_map_generation / task_72 | axil_sensor_csr

benchmarkilyasov
task_idilyasov/07_csr_register_map_generation/task_72
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260426_075435_225972_f32200

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_075435_225972_f32200 failed failed failed skipped failed extract Model response is empty
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_075435_225972_f32200__sample_1
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "model_request",
    "code": "model_request.failed",
    "message": "HTTPConnectionPool(host='ollama', port=11434): Read timed out. (read timeout=120)",
    "retryable": true,
    "details": {}
  },
  {
    "stage": "extract",
    "code": "extract.no_verilog_found",
    "message": "Model response is empty",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": false,
  "extract_ok": false,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_075435_225972_f32200 failed failed failed skipped failed extract No module/endmodule block found in model response
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_075435_225972_f32200__sample_2
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "extract",
    "code": "extract.no_verilog_found",
    "message": "No module/endmodule block found in model response",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": false,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_075435_225972_f32200 ok failed failed skipped failed syntax /data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:1: syntax error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_075435_225972_f32200__sample_3
generated.v preview 
{
  "bus": "AXI4-Lite",
  "registers": [
    {
      "name": "CTRL",
      "offset": "0x00",
      "fields": [
        {"name": "block_enable", "bits": [0, 0], "access": "RW", "reset": 0},
        {"name": "gain", "bits": [15, 8], "access": "RW", "reset": 8}
      ],
      "notes": ["writes must honor wstrb byte enables", "reserved bits read as zero"]
    },
    {
      "name": "STATUS",
      "offset": "0x04",
      "fields": [
        {"name": "irq_sticky", "bits": [0, 0], "access": "W1C", "set_on": "irq_evt"},
        {"name": "hw_level", "bits": [15, 8], "access": "RO", "source": "hw_level"}
      ]
    },
    {
      "name": "CMD",
      "offset": "0x08",
      "fields": [
        {"name": "kick", "bits": [0, 0], "access": "W1P", "pulse_output": "kick_pulse"}
      ]
    }
  ]
}
syntax details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:1: syntax error
I give up.
functional details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:1: syntax error
I give up.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/generated.v:1: syntax error\nI give up.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_3/functional/generated.v:1: syntax error\nI give up.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_075435_225972_f32200 failed failed failed skipped failed extract No module/endmodule block found in model response
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_075435_225972_f32200__sample_4
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "extract",
    "code": "extract.no_verilog_found",
    "message": "No module/endmodule block found in model response",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": false,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_075435_225972_f32200 ok failed failed skipped failed syntax /data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:1: error: Missing closing quote for string.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_075435_225972_f32200__sample_5
generated.v preview 
module" in line]
    verilog_code = "\n".join(verilog_code)

    # Remove any unused variables or wires
    verilog_code = verilog_code.split("\n")
    verilog_code = [line for line in verilog_code if "//" not in line and "wire" not in line and "reg" not in line]
    verilog_code = "\n".join(verilog_code)

    # Remove any unused modules or instances
    verilog_code = verilog_code.split("\n")
    verilog_code = [line for line in verilog_code if "//" not in line and "module" not in line and "endmodule" not in line]
    verilog_code = "\n".join(verilog_code)

    return verilog_code
[/PYTHON]
[TEST_INPUT]
{
  "bus": "AXI4-Lite",
  "registers": [
    {
      "name": "CTRL",
      "offset": "0x00",
      "fields": [
        {"name": "block_enable", "bits": [0, 0], "access": "RW", "reset": 0},
        {"name": "gain", "bits": [15, 8], "access": "RW", "reset": 8}
      ],
      "notes": ["writes must honor wstrb byte enables", "reserved bits read as zero"]
    },
    {
      "name": "STATUS",
      "offset": "0x04",
      "fields": [
...
syntax details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:1: error: Missing closing quote for string.
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:2: syntax error
I give up.
functional details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:1: error: Missing closing quote for string.
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:2: syntax error
I give up.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:1: error: Missing closing quote for string.\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:2: syntax error\nI give up.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:1: error: Missing closing quote for string.\n/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_5/functional/generated.v:2: syntax error\nI give up.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_075435_225972_f32200 ok failed failed skipped failed syntax /data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:1: syntax error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_075435_225972_f32200__sample_6
generated.v preview 
{
  "bus": "AXI4-Lite",
  "registers": [
    {
      "name": "CTRL",
      "offset": "0x00",
      "fields": [
        {"name": "block_enable", "bits": [0, 0], "access": "RW", "reset": 0},
        {"name": "gain", "bits": [15, 8], "access": "RW", "reset": 8}
      ],
      "notes": ["writes must honor wstrb byte enables", "reserved bits read as zero"]
    },
    {
      "name": "STATUS",
      "offset": "0x04",
      "fields": [
        {"name": "irq_sticky", "bits": [0, 0], "access": "W1C", "set_on": "irq_evt"},
        {"name": "hw_level", "bits": [15, 8], "access": "RO", "source": "hw_level"}
      ]
    },
    {
      "name": "CMD",
      "offset": "0x08",
      "fields": [
        {"name": "kick", "bits": [0, 0], "access": "W1P", "pulse_output": "kick_pulse"}
      ]
    }
  ]
}
syntax details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:1: syntax error
I give up.
functional details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:1: syntax error
I give up.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:1: syntax error\nI give up.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_6/functional/generated.v:1: syntax error\nI give up.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_075435_225972_f32200 ok failed failed skipped failed syntax /data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:1: syntax error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_075435_225972_f32200__sample_7
generated.v preview 
{
  "bus": "AXI4-Lite",
  "registers": [
    {
      "name": "CTRL",
      "offset": "0x00",
      "fields": [
        {"name": "block_enable", "bits": [0, 0], "access": "RW", "reset": 0},
        {"name": "gain", "bits": [15, 8], "access": "RW", "reset": 8}
      ],
      "notes": ["writes must honor wstrb byte enables", "reserved bits read as zero"]
    },
    {
      "name": "STATUS",
      "offset": "0x04",
      "fields": [
        {"name": "irq_sticky", "bits": [0, 0], "access": "W1C", "set_on": "irq_evt"},
        {"name": "hw_level", "bits": [15, 8], "access": "RO", "source": "hw_level"}
      ]
    },
    {
      "name": "CMD",
      "offset": "0x08",
      "fields": [
        {"name": "kick", "bits": [0, 0], "access": "W1P", "pulse_output": "kick_pulse"}
      ]
    }
  ]
}
syntax details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:1: syntax error
I give up.
functional details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:1: syntax error
I give up.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_7/generated.v:1: syntax error\nI give up.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_7/functional/generated.v:1: syntax error\nI give up.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_075435_225972_f32200 failed failed failed skipped failed extract No module/endmodule block found in model response
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_075435_225972_f32200__sample_8
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "extract",
    "code": "extract.no_verilog_found",
    "message": "No module/endmodule block found in model response",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": false,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_075435_225972_f32200 ok failed failed skipped failed syntax /data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:1: syntax error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_075435_225972_f32200__sample_9
generated.v preview 
{
  "bus": "AXI4-Lite",
  "registers": [
    {
      "name": "CTRL",
      "offset": "0x00",
      "fields": [
        {"name": "block_enable", "bits": [0, 0], "access": "RW", "reset": 0},
        {"name": "gain", "bits": [15, 8], "access": "RW", "reset": 8}
      ],
      "notes": ["writes must honor wstrb byte enables", "reserved bits read as zero"]
    },
    {
      "name": "STATUS",
      "offset": "0x04",
      "fields": [
        {"name": "irq_sticky", "bits": [0, 0], "access": "W1C", "set_on": "irq_evt"},
        {"name": "hw_level", "bits": [15, 8], "access": "RO", "source": "hw_level"}
      ]
    },
    {
      "name": "CMD",
      "offset": "0x08",
      "fields": [
        {"name": "kick", "bits": [0, 0], "access": "W1P", "pulse_output": "kick_pulse"}
      ]
    }
  ]
}
syntax details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:1: syntax error
I give up.
functional details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:1: syntax error
I give up.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/generated.v:1: syntax error\nI give up.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_9/functional/generated.v:1: syntax error\nI give up.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_075435_225972_f32200 ok failed failed skipped failed syntax /data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:1: syntax error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\codellama-13b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_075435_225972_f32200__sample_10
generated.v preview 
{
  "bus": "AXI4-Lite",
  "registers": [
    {
      "name": "CTRL",
      "offset": "0x00",
      "fields": [
        {"name": "block_enable", "bits": [0, 0], "access": "RW", "reset": 0},
        {"name": "gain", "bits": [15, 8], "access": "RW", "reset": 8}
      ],
      "notes": ["writes must honor wstrb byte enables", "reserved bits read as zero"]
    },
    {
      "name": "STATUS",
      "offset": "0x04",
      "fields": [
        {"name": "irq_sticky", "bits": [0, 0], "access": "W1C", "set_on": "irq_evt"},
        {"name": "hw_level", "bits": [15, 8], "access": "RO", "source": "hw_level"}
      ]
    },
    {
      "name": "CMD",
      "offset": "0x08",
      "fields": [
        {"name": "kick", "bits": [0, 0], "access": "W1P", "pulse_output": "kick_pulse"}
      ]
    }
  ]
}
syntax details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:1: syntax error
I give up.
functional details 
[stderr]
/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:1: syntax error
I give up.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/generated.v:1: syntax error\nI give up.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_075435_225972_f32200/tmp/codellama/pashencev__07_csr_register_map_generation__task_72/sample_10/functional/generated.v:1: syntax error\nI give up.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}