04_chiplet_die_to_die_integration / task_41 | ucie_flit_packager
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: Bad second flit header. Got 80, expected 81 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__04_chiplet_die_to_die_integration__task_41\samples\run_20260427_102437_171676_163c0c__sample_1
generated.v previewmodule ucie_flit_packager (
input clk,
input rst_n,
// SoC Interface (Source)
input [63:0] soc_data,
input soc_valid,
output soc_ready,
// D2D FDI Interface (Destination)
output [71:0] fdi_data,
output fdi_valid,
input fdi_ready
);
reg [63:0] soc_data_reg;
reg soc_valid_reg;
wire soc_ready_int;
reg [71:0] fdi_data_reg;
reg fdi_valid_reg;
wire fdi_ready_int;
reg [6:0] seq_num;
assign soc_ready = soc_ready_int;
assign fdi_valid = fdi_valid_reg;
assign fdi_data = fdi_data_reg;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
seq_num <= 7'b0000000;
soc_valid_reg <= 1'b0;
fdi_valid_reg <= 1'b0;
soc_data_reg <= 64'b0;
end else begin
...
functional details[stdout]
ERROR: Bad second flit header. Got 80, expected 81
ERROR: Flit header corrupted upon immediate backpressure.
ERROR: Sequence Runaway Detected! The wrapper incremented seq_num
even though fdi_ready was 0. Header is now 80, expected 82
ERROR: Sequence failed to resume properly after backpressure.
TEST_FAILED
/workspace/banchmarks/pashencev/04_chiplet_die_to_die_integration/task_41/tb.v:103: $finish called at 66000 (1ps)
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: Bad second flit header. Got 80, expected 81",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: Bad first flit header. Got xx, expected 80 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__04_chiplet_die_to_die_integration__task_41\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v previewmodule ucie_flit_packager (
input clk,
input rst_n,
// SoC Interface (Source)
input [63:0] soc_data,
input soc_valid,
output reg soc_ready,
// D2D FDI Interface (Destination)
output reg [71:0] fdi_data,
output reg fdi_valid,
input fdi_ready
);
reg [63:0] packet;
reg valid_packet;
reg [6:0] seq_num;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
seq_num <= 7'b0000000;
soc_ready <= 1'b0;
fdi_valid <= 1'b0;
packet <= 64'd0;
valid_packet <= 1'b0;
end else begin
if (soc_valid && fdi_ready) begin
// Pack the data into a 72-bit flit with header and sequence number
fdi_data <= {1'b1, seq_num, soc_data[63:8], soc_data[7]};
packet <= soc_data;
valid_packet <= 1'b1;
// Increment the sequence number
seq_num <= seq_num + 1'b1;
...
functional details[stdout]
ERROR: Bad first flit header. Got xx, expected 80
ERROR: Bad second flit header. Got 01, expected 81
ERROR: Flit header corrupted upon immediate backpressure.
ERROR: Sequence Runaway Detected! The wrapper incremented seq_num
even though fdi_ready was 0. Header is now 01, expected 82
ERROR: Sequence failed to resume properly after backpressure.
TEST_FAILED
/workspace/banchmarks/pashencev/04_chiplet_die_to_die_integration/task_41/tb.v:103: $finish called at 66000 (1ps)
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: Bad first flit header. Got xx, expected 80",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_102437_171676_163c0c | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__04_chiplet_die_to_die_integration__task_41\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v previewmodule ucie_flit_packager (
input clk,
input rst_n,
// SoC Interface (Source)
input [63:0] soc_data,
input soc_valid,
output reg soc_ready,
// D2D FDI Interface (Destination)
output reg [71:0] fdi_data,
output reg fdi_valid,
input fdi_ready
);
reg [63:0] data_buffer;
reg valid_buffer;
reg ready_buffer;
reg [6:0] seq_num;
wire handshake;
assign handshake = soc_valid & fdi_ready;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_buffer <= 64'b0;
valid_buffer <= 1'b0;
seq_num <= 7'b0;
end else if (handshake) begin
data_buffer <= soc_data;
valid_buffer <= 1'b1;
if (seq_num == 7'd127) begin
seq_num <= 7'b0;
end else begin
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/04_chiplet_die_to_die_integration/task_41/tb.v:103: $finish called at 66000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_4 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: Bad first flit header. Got 00, expected 80 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__04_chiplet_die_to_die_integration__task_41\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v previewmodule ucie_flit_packager (
input clk,
input rst_n,
// SoC Interface (Source)
input [63:0] soc_data,
input soc_valid,
output reg soc_ready,
// D2D FDI Interface (Destination)
output reg [71:0] fdi_data,
output reg fdi_valid,
input fdi_ready
);
reg [63:0] data_buffer;
reg valid_buffer;
wire handshake;
reg [6:0] seq_num;
assign handshake = soc_valid & fdi_ready;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_buffer <= 64'b0;
valid_buffer <= 1'b0;
seq_num <= 7'b0;
end else if (handshake) begin
data_buffer <= soc_data;
valid_buffer <= 1'b1;
seq_num <= seq_num + 1;
if (seq_num == 7'd127) begin
seq_num <= 7'b0;
end
...
functional details[stdout]
ERROR: Bad first flit header. Got 00, expected 80
ERROR: Bad second flit header. Got 01, expected 81
ERROR: Flit header corrupted upon immediate backpressure.
ERROR: Sequence Runaway Detected! The wrapper incremented seq_num
even though fdi_ready was 0. Header is now 02, expected 82
ERROR: Sequence failed to resume properly after backpressure.
TEST_FAILED
/workspace/banchmarks/pashencev/04_chiplet_die_to_die_integration/task_41/tb.v:103: $finish called at 66000 (1ps)
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: Bad first flit header. Got 00, expected 80",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: Bad first flit header. Got 00, expected 80 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__04_chiplet_die_to_die_integration__task_41\samples\run_20260427_102437_171676_163c0c__sample_5
generated.v previewmodule ucie_flit_packager (
input clk,
input rst_n,
// SoC Interface (Source)
input [63:0] soc_data,
input soc_valid,
output soc_ready,
// D2D FDI Interface (Destination)
output [71:0] fdi_data,
output fdi_valid,
input fdi_ready
);
reg [63:0] data_reg;
reg valid_reg;
wire ready_wire;
reg [71:0] flit_data;
reg valid_flit;
reg [6:0] seq_num;
reg [6:0] next_seq_num;
assign soc_ready = fdi_ready;
assign fdi_valid = valid_reg;
assign fdi_data = flit_data;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
seq_num <= 7'b0000000;
data_reg <= 64'b0;
valid_reg <= 1'b0;
end else if (soc_valid && fdi_ready) begin
data_reg <= soc_data;
...
functional details[stdout]
ERROR: Bad first flit header. Got 00, expected 80
ERROR: Bad second flit header. Got 01, expected 81
ERROR: Flit header corrupted upon immediate backpressure.
ERROR: Sequence Runaway Detected! The wrapper incremented seq_num
even though fdi_ready was 0. Header is now 00, expected 82
ERROR: Sequence failed to resume properly after backpressure.
TEST_FAILED
/workspace/banchmarks/pashencev/04_chiplet_die_to_die_integration/task_41/tb.v:103: $finish called at 66000 (1ps)
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: Bad first flit header. Got 00, expected 80",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:25: error: temp_soc_ready is not a valid l-value in ucie_flit_packager. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__04_chiplet_die_to_die_integration__task_41\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v previewmodule ucie_flit_packager (
input clk,
input rst_n,
// SoC Interface (Source)
input [63:0] soc_data,
input soc_valid,
output reg soc_ready,
// D2D FDI Interface (Destination)
output reg [71:0] fdi_data,
output reg fdi_valid,
input fdi_ready
);
reg [63:0] temp_soc_data;
reg temp_soc_valid;
wire temp_soc_ready;
reg [71:0] temp_fdi_data;
reg temp_fdi_valid;
wire temp_fdi_ready;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
fdi_data <= 72'b1_0000000; // Hardcoded header with bit 71 set to 1
fdi_valid <= 0;
temp_soc_ready <= 0;
end else begin
if (fdi_ready && soc_valid) begin
fdi_data <= {8'b1_0000000, soc_data}; // Construct the flit with header and data
fdi_valid <= 1;
temp_soc_ready <= 0;
end else if (fdi_ready) begin
fdi_data <= {8'b1_0000000, soc_data}; // Construct the flit with header and data
...
syntax details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:25: error: temp_soc_ready is not a valid l-value in ucie_flit_packager. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:16: : temp_soc_ready is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:30: error: temp_soc_ready is not a valid l-value in ucie_flit_packager. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:16: : temp_soc_ready is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:34: error: temp_soc_ready is not a valid l-value in ucie_flit_packager. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:16: : temp_soc_ready is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:37: error: temp_soc_ready is not a valid l-value in ucie_flit_packager. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:16: : temp_soc_ready is declared here as wire. 4 error(s) during elaboration. functional details[stderr] /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:25: error: temp_soc_ready is not a valid l-value in tb_task_41.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:16: : temp_soc_ready is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:30: error: temp_soc_ready is not a valid l-value in tb_task_41.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:16: : temp_soc_ready is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:34: error: temp_soc_ready is not a valid l-value in tb_task_41.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:16: : temp_soc_ready is declared here as wire. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:37: error: temp_soc_ready is not a valid l-value in tb_task_41.dut. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:16: : temp_soc_ready is declared here as wire. 4 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:25: error: temp_soc_ready is not a valid l-value in ucie_flit_packager.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:16: : temp_soc_ready is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:30: error: temp_soc_ready is not a valid l-value in ucie_flit_packager.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:16: : temp_soc_ready is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:34: error: temp_soc_ready is not a valid l-value in ucie_flit_packager.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:16: : temp_soc_ready is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:37: error: temp_soc_ready is not a valid l-value in ucie_flit_packager.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/generated.v:16: : temp_soc_ready is declared here as wire.\n4 error(s) during elaboration.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:25: error: temp_soc_ready is not a valid l-value in tb_task_41.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:16: : temp_soc_ready is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:30: error: temp_soc_ready is not a valid l-value in tb_task_41.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:16: : temp_soc_ready is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:34: error: temp_soc_ready is not a valid l-value in tb_task_41.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:16: : temp_soc_ready is declared here as wire.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:37: error: temp_soc_ready is not a valid l-value in tb_task_41.dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__04_chiplet_die_to_die_integration__task_41/sample_6/functional/generated.v:16: : temp_soc_ready is declared here as wire.\n4 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: Bad first flit header. Got 0X, expected 80 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__04_chiplet_die_to_die_integration__task_41\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v previewmodule ucie_flit_packager (
input clk,
input rst_n,
// SoC Interface (Source)
input [63:0] soc_data,
input soc_valid,
output reg soc_ready,
// D2D FDI Interface (Destination)
output reg [71:0] fdi_data,
output reg fdi_valid,
input fdi_ready
);
reg [63:0] packet;
reg header;
reg [6:0] seq_num;
reg valid_packet;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
soc_ready <= 1'b0;
fdi_valid <= 1'b0;
seq_num <= 7'b0000000;
valid_packet <= 1'b0;
end else begin
if (soc_valid && fdi_ready) begin
packet <= soc_data;
header <= 1'b1; // Hardcoded to 1 for valid data flit
seq_num <= seq_num + 1;
if (seq_num == 7'd127) begin
seq_num <= 7'b0000000;
end
...
functional details[stdout]
ERROR: Bad first flit header. Got 0X, expected 80
ERROR: Bad second flit header. Got 0X, expected 81
ERROR: Flit header corrupted upon immediate backpressure.
ERROR: Sequence Runaway Detected! The wrapper incremented seq_num
even though fdi_ready was 0. Header is now 01, expected 82
ERROR: Sequence failed to resume properly after backpressure.
TEST_FAILED
/workspace/banchmarks/pashencev/04_chiplet_die_to_die_integration/task_41/tb.v:103: $finish called at 66000 (1ps)
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: Bad first flit header. Got 0X, expected 80",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: Bad first flit header. Got 01, expected 80 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__04_chiplet_die_to_die_integration__task_41\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v previewmodule ucie_flit_packager (
input clk,
input rst_n,
// SoC Interface (Source)
input [63:0] soc_data,
input soc_valid,
output soc_ready,
// D2D FDI Interface (Destination)
output [71:0] fdi_data,
output fdi_valid,
input fdi_ready
);
reg [63:0] soc_data_reg;
reg soc_valid_reg;
wire soc_ready_int;
reg [71:0] fdi_data_reg;
reg fdi_valid_reg;
wire fdi_ready_int;
reg [6:0] seq_num;
assign soc_ready = soc_ready_int;
assign fdi_valid = fdi_valid_reg;
assign fdi_data = fdi_data_reg;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
seq_num <= 7'b0000000;
soc_data_reg <= 64'b0;
soc_valid_reg <= 1'b0;
fdi_data_reg <= {8'b1, 64'b0};
fdi_valid_reg <= 1'b0;
...
functional details[stdout]
ERROR: Bad first flit header. Got 01, expected 80
ERROR: Bad second flit header. Got 01, expected 81
ERROR: Flit header corrupted upon immediate backpressure.
ERROR: Sequence Runaway Detected! The wrapper incremented seq_num
even though fdi_ready was 0. Header is now 01, expected 82
ERROR: Sequence failed to resume properly after backpressure.
TEST_FAILED
/workspace/banchmarks/pashencev/04_chiplet_die_to_die_integration/task_41/tb.v:103: $finish called at 66000 (1ps)
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: Bad first flit header. Got 01, expected 80",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260427_102437_171676_163c0c | ok | ok | failed | skipped | failed | functional | error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__04_chiplet_die_to_die_integration__task_41\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v previewmodule ucie_flit_packager (
input clk,
input rst_n,
// SoC Interface (Source)
input [63:0] soc_data,
input soc_valid,
output reg soc_ready,
// D2D FDI Interface (Destination)
output reg [71:0] fdi_data,
output reg fdi_valid,
input fdi_ready
);
reg [63:0] data_buffer;
reg valid_buffer;
wire handshake;
reg [6:0] seq_num;
assign handshake = soc_valid & fdi_ready;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_buffer <= 64'b0;
valid_buffer <= 1'b0;
seq_num <= 7'b0;
end else if (handshake) begin
data_buffer <= soc_data;
valid_buffer <= 1'b1;
seq_num <= seq_num + 1;
end else if (!fdi_ready) begin
valid_buffer <= 1'b0;
end
...
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_error",
"message": "error",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: Bad first flit header. Got xx, expected 80 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__04_chiplet_die_to_die_integration__task_41\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v previewmodule ucie_flit_packager (
input clk,
input rst_n,
// SoC Interface (Source)
input [63:0] soc_data,
input soc_valid,
output soc_ready,
// D2D FDI Interface (Destination)
output [71:0] fdi_data,
output fdi_valid,
input fdi_ready
);
reg [63:0] data_reg;
reg valid_reg;
wire ready_sig;
reg [6:0] seq_num;
reg [71:0] flit;
assign soc_ready = fdi_ready;
assign fdi_valid = valid_reg;
assign fdi_data = flit;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_reg <= 64'b0;
valid_reg <= 1'b0;
seq_num <= 7'b0;
end else begin
if (soc_valid && fdi_ready) begin
data_reg <= soc_data;
valid_reg <= 1'b1;
...
functional details[stdout]
ERROR: Bad first flit header. Got xx, expected 80
ERROR: Bad second flit header. Got 80, expected 81
ERROR: Flit header corrupted upon immediate backpressure.
ERROR: Sequence Runaway Detected! The wrapper incremented seq_num
even though fdi_ready was 0. Header is now 81, expected 82
ERROR: Sequence failed to resume properly after backpressure.
TEST_FAILED
/workspace/banchmarks/pashencev/04_chiplet_die_to_die_integration/task_41/tb.v:103: $finish called at 66000 (1ps)
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: Bad first flit header. Got xx, expected 80",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|