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deepseek-coder-v2:16b | RAG off

05_dft_testability / task_51 | scan_reset_override_reg

benchmarkilyasov
task_idilyasov/05_dft_testability/task_51
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260427_102437_171676_163c0c

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_102437_171676_163c0c__sample_1
generated.v preview 
module scan_reset_override_reg (
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        if (!test_mode) begin
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            data_out <= data_out;
            scan_out <= scan_out;
        end
    end else if (!test_mode) begin
        if (load_en) begin
            data_out <= data_in;
        end
        scan_out <= data_out[3];
    end else begin
        data_out <= data_out;
        scan_out <= scan_out;
    end
end

endmodule
functional details 
[stderr]
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
1 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260427_102437_171676_163c0c ok failed failed skipped failed syntax /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_2/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v preview 
module scan_reset_override_reg (
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        if (!test_mode) begin
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            data_out <= data_out;
            scan_out <= 1'b0;
        end
    end else if (!test_mode) begin
        if (load_en) begin
            data_out <= data_in;
        end
        scan_out <= data_out[3];
    end else if (scan_en) begin
        data_out <= {data_out[2:0], scan_in};
        scan_out <= data_out[3];
    end
end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_2/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'
1 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_2/functional/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `tb_task_51.dut'
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_2/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_2/functional/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `tb_task_51.dut'\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260427_102437_171676_163c0c ok failed failed skipped failed syntax /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_3/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v preview 
module scan_reset_override_reg (
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        if (!test_mode) begin
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            data_out <= data_out;
            scan_out <= 1'b0;
        end
    end else if (!test_mode) begin
        if (load_en) begin
            data_out <= data_in;
        end
        scan_out <= data_out[3];
    end else if (scan_en) begin
        data_out <= {data_out[2:0], scan_in};
        scan_out <= data_out[3];
    end
end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_3/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'
1 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_3/functional/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `tb_task_51.dut'
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_3/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_3/functional/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `tb_task_51.dut'\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260427_102437_171676_163c0c ok failed failed skipped failed syntax /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_4/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v preview 
module scan_reset_override_reg (
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        if (!test_mode) begin
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            data_out <= data_out;
            scan_out <= 1'b0;
        end
    end else if (!test_mode) begin
        if (load_en) begin
            data_out <= data_in;
        end
        scan_out <= data_out[3];
    end else if (scan_en) begin
        data_out <= {data_out[2:0], scan_in};
        scan_out <= data_out[3];
    end
end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_4/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'
1 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_4/functional/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `tb_task_51.dut'
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_4/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_4/functional/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `tb_task_51.dut'\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260427_102437_171676_163c0c ok failed failed skipped failed syntax /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_5/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_102437_171676_163c0c__sample_5
generated.v preview 
module scan_reset_override_reg (
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        if (!test_mode) begin
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            data_out <= data_out;
            scan_out <= 1'b0;
        end
    end else if (!test_mode) begin
        if (load_en) begin
            data_out <= data_in;
        end
        scan_out <= data_out[3];
    end else if (scan_en) begin
        data_out <= {data_out[2:0], scan_in};
        scan_out <= data_out[3];
    end
end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_5/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'
1 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_5/functional/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `tb_task_51.dut'
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_5/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_5/functional/generated.v:27: error: Unable to bind wire/reg/memory `scan_in' in `tb_task_51.dut'\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v preview 
module scan_reset_override_reg (
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        if (!test_mode) begin
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            data_out <= data_out;
            scan_out <= 1'b0;
        end
    end else if (!test_mode) begin
        if (load_en) begin
            data_out <= data_in;
        end
        scan_out <= data_out[3];
    end else begin
        data_out <= data_out;
        scan_out <= 1'b0;
    end
end

endmodule
functional details 
[stderr]
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
1 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260427_102437_171676_163c0c ok failed failed skipped failed syntax /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_7/generated.v:19: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v preview 
module scan_reset_override_reg (
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n || test_mode) begin
        data_out <= 4'b0;
        scan_out <= 1'b0;
    end else if (load_en) begin
        data_out <= data_in;
    end else if (scan_en && !test_mode) begin
        data_out <= {data_out[2:0], scan_in};
    end
end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_7/generated.v:19: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'
1 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_7/functional/generated.v:19: error: Unable to bind wire/reg/memory `scan_in' in `tb_task_51.dut'
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_7/generated.v:19: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_7/functional/generated.v:19: error: Unable to bind wire/reg/memory `scan_in' in `tb_task_51.dut'\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260427_102437_171676_163c0c ok failed failed skipped failed syntax /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_8/generated.v:20: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v preview 
module scan_reset_override_reg (
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n || test_mode) begin
        data_out <= 4'b0;
        scan_out <= 1'b0;
    end else if (load_en) begin
        data_out <= data_in;
        scan_out <= data_out[3];
    end else if (scan_en && !load_en) begin
        data_out <= {data_out[2:0], scan_in};
        scan_out <= data_out[3];
    end
end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_8/generated.v:20: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'
1 error(s) during elaboration.
functional details 
[stderr]
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_8/functional/generated.v:20: error: Unable to bind wire/reg/memory `scan_in' in `tb_task_51.dut'
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_8/generated.v:20: error: Unable to bind wire/reg/memory `scan_in' in `scan_reset_override_reg'\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_51/sample_8/functional/generated.v:20: error: Unable to bind wire/reg/memory `scan_in' in `tb_task_51.dut'\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v preview 
module scan_reset_override_reg (
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        if (!test_mode) begin
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            data_out <= data_out;
            scan_out <= 1'b0;
        end
    end else if (!test_mode) begin
        if (load_en) begin
            data_out <= data_in;
        end
        scan_out <= data_out[3];
    end else begin
        data_out <= data_out;
        scan_out <= 1'b0;
    end
end

endmodule
functional details 
[stderr]
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
1 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_51\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v preview 
module scan_reset_override_reg (
    input clk,
    input rst_n,
    input test_mode,
    input scan_en,
    input load_en,
    input [3:0] data_in,
    output reg [3:0] data_out,
    output reg scan_out
);

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        if (!test_mode) begin
            data_out <= 4'b0;
            scan_out <= 1'b0;
        end else begin
            data_out <= data_out;
            scan_out <= 1'b0;
        end
    end else if (!test_mode) begin
        if (load_en) begin
            data_out <= data_in;
        end
        scan_out <= data_out[3];
    end else begin
        data_out <= data_out;
        scan_out <= 1'b0;
    end
end

endmodule
functional details 
[stderr]
/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.
1 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/pashencev/05_dft_testability/task_51/tb.v:18: error: port ``scan_in'' is not a port of dut.\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}