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deepseek-coder-v2:16b | RAG off

05_dft_testability / task_52 | jtag_tap_debug

benchmarkilyasov
task_idilyasov/05_dft_testability/task_52
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260427_102437_171676_163c0c

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260427_102437_171676_163c0c ok failed failed skipped failed syntax /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260427_102437_171676_163c0c__sample_1
generated.v preview
module jtag_tap_debug (
    input tck,
    input trst_n,
    input tms,
    input tdi,
    output reg tdo,
    input [7:0] dbg_status,
    output reg [7:0] dbg_control
);

reg [3:0] ir;
reg [7:0] dr;
reg shift_dr, update_dr, capture_ir, shift_ir, update_ir;

always @(posedge tck or negedge trst_n) begin
    if (!trst_n) begin
        ir <= 4'b0001; // IDCODE
        dr <= 8'h00;
        dbg_control <= 8'h00;
        shift_dr <= 0;
        update_dr <= 0;
        capture_ir <= 0;
        shift_ir <= 0;
        update_ir <= 0;
    end else begin
        if (capture_ir) ir <= {tms, ir[3:1]};
        if (shift_ir) ir <= {tdi, ir[3:1]};
        if (update_ir) ir <= ir;

        if (capture_dr) dr <= 8'hA5; // Load IDCODE value
        if (shift_dr) dr <= {tdi, dr[7:1]};
        if (update_dr) dr <= dr;
...
syntax details
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/generated.v:30: error: Unable to elaborate condition expression.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/generated.v:41: error: Could not find variable ``capture_dr'' in ``jtag_tap_debug''
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/generated.v:46: error: Could not find variable ``capture_dr'' in ``jtag_tap_debug''
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/generated.v:54: error: Could not find variable ``capture_dr'' in ``jtag_tap_debug''
5 error(s) during elaboration.
functional details
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/functional/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/functional/generated.v:30: error: Unable to elaborate condition expression.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/functional/generated.v:41: error: Could not find variable ``capture_dr'' in ``tb_task_52.dut''
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/functional/generated.v:46: error: Could not find variable ``capture_dr'' in ``tb_task_52.dut''
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/functional/generated.v:54: error: Could not find variable ``capture_dr'' in ``tb_task_52.dut''
5 error(s) during elaboration.
synthesis details
[error]
None
errors[]
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/generated.v:30: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/generated.v:41: error: Could not find variable ``capture_dr'' in ``jtag_tap_debug''\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/generated.v:46: error: Could not find variable ``capture_dr'' in ``jtag_tap_debug''\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/generated.v:54: error: Could not find variable ``capture_dr'' in ``jtag_tap_debug''\n5 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/functional/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/functional/generated.v:30: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/functional/generated.v:41: error: Could not find variable ``capture_dr'' in ``tb_task_52.dut''\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/functional/generated.v:46: error: Could not find variable ``capture_dr'' in ``tb_task_52.dut''\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_1/functional/generated.v:54: error: Could not find variable ``capture_dr'' in ``tb_task_52.dut''\n5 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260427_102437_171676_163c0c ok failed failed skipped failed syntax /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v preview
module jtag_tap_debug (
    input tck,
    input trst_n,
    input tms,
    input tdi,
    output reg tdo,
    input [7:0] dbg_status,
    output reg [7:0] dbg_control
);

reg [3:0] ir;
reg [7:0] dr;
reg shift_dr, update_dr, capture_ir, shift_ir, update_ir;

always @(posedge tck or negedge trst_n) begin
    if (!trst_n) begin
        ir <= 4'b0001; // IDCODE
        dr <= 8'h00;
        dbg_control <= 8'h00;
        shift_dr <= 0;
        update_dr <= 0;
        capture_ir <= 0;
        shift_ir <= 0;
        update_ir <= 0;
        tdo <= 0;
    end else begin
        if (capture_ir) ir <= {tms, ir[3:1]};
        if (shift_ir) ir <= {tdi, ir[3:1]};
        if (update_ir) ir <= ir;
        if (capture_dr) dr <= 8'hA5; // IDCODE instruction
        else if (shift_dr) dr <= {tdi, dr[7:1]};
        else if (update_dr) dr <= dr;
...
syntax details
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:30: error: Unable to elaborate condition expression.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:91: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:91: error: Unable to elaborate condition expression.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:96: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:96: error: Unable to elaborate condition expression.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:101: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:101: error: Unable to elaborate condition expression.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:106: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:106: error: Unable to elaborate condition expression.
10 error(s) during elaboration.
functional details
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:30: error: Unable to elaborate condition expression.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:91: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:91: error: Unable to elaborate condition expression.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:96: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:96: error: Unable to elaborate condition expression.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:101: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:101: error: Unable to elaborate condition expression.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:106: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:106: error: Unable to elaborate condition expression.
10 error(s) during elaboration.
synthesis details
[error]
None
errors[]
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:30: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:91: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:91: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:96: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:96: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:101: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:101: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:106: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/generated.v:106: error: Unable to elaborate condition expression.\n10 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:30: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:91: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:91: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:96: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:96: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:101: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:101: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:106: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_2/functional/generated.v:106: error: Unable to elaborate condition expression.\n10 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260427_102437_171676_163c0c ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 00
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v preview
module jtag_tap_debug (
    input tck,
    input trst_n,
    input tms,
    input tdi,
    output reg tdo,
    input [7:0] dbg_status,
    output reg [7:0] dbg_control
);

reg [3:0] ir;
reg [7:0] dr;
reg shift_dr, update_ir, update_dr;

always @(posedge tck or negedge trst_n) begin
    if (!trst_n) begin
        ir <= 4'b0001; // IDCODE
        dbg_control <= 8'h00;
        dr <= 8'h00;
        shift_dr <= 0;
        update_ir <= 0;
        update_dr <= 0;
        tdo <= 0;
    end else begin
        if (tms == 1'b1) begin
            case (ir)
                4'b0001: // IDCODE
                    dbg_control <= 8'hA5;
                4'b0010: // DBG_CTL
                    dr <= dbg_control;
                4'b0011: // DBG_STAT
                    dr <= dbg_status;
...
functional details
[stdout]
ERROR: IDCODE readback failed. Expected A5, got 00
ERROR: IDCODE scan unexpectedly modified dbg_control.
ERROR: initial DBG_CTL scan should have shifted out 00, got 02
ERROR: DBG_CTL update failed. Expected 3C, got a5
ERROR: DBG_CTL readback failed. Expected 3C, got 03
ERROR: DBG_CTL readback corrupted dbg_control.
ERROR: DBG_STAT readback failed. Expected 96, got 03
ERROR: DBG_STAT access unexpectedly modified dbg_control.
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 00",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260427_102437_171676_163c0c ok failed failed skipped failed syntax /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v preview
module jtag_tap_debug (
    input tck,
    input trst_n,
    input tms,
    input tdi,
    output reg tdo,
    input [7:0] dbg_status,
    output reg [7:0] dbg_control
);

reg [3:0] ir;
reg [7:0] dr;
reg shift_dr, update_dr, capture_ir, shift_ir, update_ir;

always @(posedge tck or negedge trst_n) begin
    if (!trst_n) begin
        ir <= 4'b0001; // IDCODE
        dr <= 8'h00;
        dbg_control <= 8'h00;
        shift_dr <= 0;
        update_dr <= 0;
        capture_ir <= 0;
        shift_ir <= 0;
        update_ir <= 0;
        tdo <= 0;
    end else begin
        if (capture_ir) ir <= {tms, ir[3:1]};
        if (shift_ir) ir <= {tdi, ir[3:1]};
        if (update_ir) ir <= ir;
        if (capture_dr) dr <= 8'hA5; // IDCODE instruction specific
        if (shift_dr) dr <= {tdi, dr[7:1]};
        if (update_dr) dr <= dr;
...
syntax details
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/generated.v:30: error: Unable to elaborate condition expression.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/generated.v:36: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/generated.v:38: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/generated.v:40: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'
5 error(s) during elaboration.
functional details
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/functional/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/functional/generated.v:30: error: Unable to elaborate condition expression.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/functional/generated.v:36: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/functional/generated.v:38: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/functional/generated.v:40: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'
5 error(s) during elaboration.
synthesis details
[error]
None
errors[]
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/generated.v:30: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/generated.v:36: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/generated.v:38: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/generated.v:40: error: Unable to bind wire/reg/memory `capture_dr' in `jtag_tap_debug'\n5 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/functional/generated.v:30: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/functional/generated.v:30: error: Unable to elaborate condition expression.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/functional/generated.v:36: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/functional/generated.v:38: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_4/functional/generated.v:40: error: Unable to bind wire/reg/memory `capture_dr' in `tb_task_52.dut'\n5 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260427_102437_171676_163c0c failed failed failed skipped failed extract Model response is empty
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260427_102437_171676_163c0c__sample_5
synthesis details
[error]
None
errors[]
[
  {
    "stage": "model_request",
    "code": "model_request.failed",
    "message": "HTTPConnectionPool(host='ollama', port=11434): Read timed out. (read timeout=120)",
    "retryable": true,
    "details": {}
  },
  {
    "stage": "extract",
    "code": "extract.no_verilog_found",
    "message": "Model response is empty",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": false,
  "extract_ok": false,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260427_102437_171676_163c0c ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 00
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v preview
module jtag_tap_debug (
    input tck,
    input trst_n,
    input tms,
    input tdi,
    output reg tdo,
    input [7:0] dbg_status,
    output reg [7:0] dbg_control
);

reg [3:0] ir;
reg [7:0] dr;
reg shift_dr, update_dr, capture_dr, shift_ir, update_ir, capture_ir;

always @(posedge tck or negedge trst_n) begin
    if (!trst_n) begin
        ir <= 4'b0001; // IDCODE
        dr <= 8'h00;
        dbg_control <= 8'h00;
        shift_dr <= 0;
        update_dr <= 0;
        capture_dr <= 0;
        shift_ir <= 0;
        update_ir <= 0;
        capture_ir <= 0;
        tdo <= 0;
    end else begin
        if (capture_ir) ir <= {tdi, ir[3:1]};
        if (shift_ir) ir <= {tdi, ir[3:1]};
        if (update_ir) ir <= ir;
        if (capture_dr) dr <= {tdi, dr[7:1]};
        if (shift_dr) dr <= {tdi, dr[7:1]};
...
functional details
[stdout]
ERROR: IDCODE readback failed. Expected A5, got 00
ERROR: DBG_CTL update failed. Expected 3C, got 00
ERROR: DBG_CTL readback failed. Expected 3C, got 00
ERROR: DBG_CTL readback corrupted dbg_control.
ERROR: DBG_STAT readback failed. Expected 96, got 00
ERROR: DBG_STAT access unexpectedly modified dbg_control.
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 00",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260427_102437_171676_163c0c ok failed failed skipped failed syntax /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/generated.v:20: error: shift_dr Unable to assign to unresolved wires.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v preview
module jtag_tap_debug (
    input tck,
    input trst_n,
    input tms,
    input tdi,
    output reg tdo,
    input [7:0] dbg_status,
    output reg [7:0] dbg_control
);

reg [3:0] ir;
reg [7:0] dr;
reg shift_dr, update_dr, capture_ir, shift_ir, update_ir;

always @(posedge tck or negedge trst_n) begin
    if (!trst_n) begin
        ir <= 4'b0001; // IDCODE
        dr <= 8'h00;
        dbg_control <= 8'h00;
        shift_dr <= 0;
        update_dr <= 0;
        capture_ir <= 0;
        shift_ir <= 0;
        update_ir <= 0;
    end else begin
        if (capture_ir) ir <= {tms, ir[3:1]};
        if (shift_ir) ir <= {tdi, ir[3:1]};
        if (update_ir) ir <= ir;

        if (capture_dr) dr <= 8'hA5; // IDCODE instruction
        else if (shift_dr) dr <= {tdi, dr[7:1]};
        else if (update_dr) dr <= dr;
...
syntax details
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/generated.v:20: error: shift_dr Unable to assign to unresolved wires.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/generated.v:21: error: update_dr Unable to assign to unresolved wires.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/generated.v:22: error: capture_ir Unable to assign to unresolved wires.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/generated.v:23: error: shift_ir Unable to assign to unresolved wires.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/generated.v:24: error: update_ir Unable to assign to unresolved wires.
5 error(s) during elaboration.
functional details
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/functional/generated.v:20: error: shift_dr Unable to assign to unresolved wires.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/functional/generated.v:21: error: update_dr Unable to assign to unresolved wires.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/functional/generated.v:22: error: capture_ir Unable to assign to unresolved wires.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/functional/generated.v:23: error: shift_ir Unable to assign to unresolved wires.
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/functional/generated.v:24: error: update_ir Unable to assign to unresolved wires.
5 error(s) during elaboration.
synthesis details
[error]
None
errors[]
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/generated.v:20: error: shift_dr Unable to assign to unresolved wires.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/generated.v:21: error: update_dr Unable to assign to unresolved wires.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/generated.v:22: error: capture_ir Unable to assign to unresolved wires.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/generated.v:23: error: shift_ir Unable to assign to unresolved wires.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/generated.v:24: error: update_ir Unable to assign to unresolved wires.\n5 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/functional/generated.v:20: error: shift_dr Unable to assign to unresolved wires.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/functional/generated.v:21: error: update_dr Unable to assign to unresolved wires.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/functional/generated.v:22: error: capture_ir Unable to assign to unresolved wires.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/functional/generated.v:23: error: shift_ir Unable to assign to unresolved wires.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__05_dft_testability__task_52/sample_7/functional/generated.v:24: error: update_ir Unable to assign to unresolved wires.\n5 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260427_102437_171676_163c0c ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 00
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v preview
module jtag_tap_debug (
    input tck,
    input trst_n,
    input tms,
    input tdi,
    output reg tdo,
    input [7:0] dbg_status,
    output reg [7:0] dbg_control
);

reg [3:0] ir;
reg [7:0] dr;
reg shift_dr, update_ir, update_dr;

always @(posedge tck or negedge trst_n) begin
    if (!trst_n) begin
        ir <= 4'b0001; // IDCODE
        dbg_control <= 8'h00;
        dr <= 8'h00;
        shift_dr <= 0;
        update_ir <= 0;
        update_dr <= 0;
    end else begin
        if (tms) begin
            case (ir)
                4'b0001: ir <= 4'b0001; // IDCODE
                4'b0010: ir <= 4'b0010; // DBG_CTL
                4'b0011: ir <= 4'b0011; // DBG_STAT
                default: ir <= 4'b0001; // Default to IDCODE
            endcase
        end else begin
            case (ir)
...
functional details
[stdout]
ERROR: IDCODE readback failed. Expected A5, got 00
ERROR: DBG_CTL update failed. Expected 3C, got 00
ERROR: DBG_CTL readback failed. Expected 3C, got 00
ERROR: DBG_CTL readback corrupted dbg_control.
ERROR: DBG_STAT readback failed. Expected 96, got 00
ERROR: DBG_STAT access unexpectedly modified dbg_control.
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 00",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260427_102437_171676_163c0c ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 00
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v preview
module jtag_tap_debug (
    input tck,
    input trst_n,
    input tms,
    input tdi,
    output reg tdo,
    input [7:0] dbg_status,
    output reg [7:0] dbg_control
);

reg [3:0] ir;
reg [7:0] dr;
reg shift_dr, update_ir, update_dr;

always @(posedge tck or negedge trst_n) begin
    if (!trst_n) begin
        ir <= 4'b0001; // IDCODE
        dbg_control <= 8'h00;
        dr <= 8'h00;
        shift_dr <= 0;
        update_ir <= 0;
        update_dr <= 0;
    end else begin
        if (tms) begin
            case (ir)
                4'b0001: ir <= tdi ? 4'b0001 : 4'b0000; // IDCODE
                4'b0010: ir <= tdi ? 4'b0010 : 4'b0000; // DBG_CTL
                4'b0011: ir <= tdi ? 4'b0011 : 4'b0000; // DBG_STAT
                default: ir <= 4'b0000; // Other instructions reset IR to IDCODE
            endcase
        end else begin
            if (ir == 4'b0001) begin
...
functional details
[stdout]
ERROR: IDCODE readback failed. Expected A5, got 00
ERROR: DBG_CTL update failed. Expected 3C, got 00
ERROR: DBG_CTL readback failed. Expected 3C, got 00
ERROR: DBG_CTL readback corrupted dbg_control.
ERROR: DBG_STAT readback failed. Expected 96, got 00
ERROR: DBG_STAT access unexpectedly modified dbg_control.
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 00",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260427_102437_171676_163c0c ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 54
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v preview
module jtag_tap_debug (
    input tck,
    input trst_n,
    input tms,
    input tdi,
    output reg tdo,
    input [7:0] dbg_status,
    output reg [7:0] dbg_control
);

reg [3:0] ir;
reg [7:0] dr;
reg shift_dr, update_ir, update_dr;

always @(posedge tck or negedge trst_n) begin
    if (!trst_n) begin
        ir <= 4'b0001; // IDCODE
        dbg_control <= 8'h00;
        dr <= 8'h00;
        shift_dr <= 0;
        update_ir <= 0;
        update_dr <= 0;
    end else begin
        if (tms) begin
            case (ir)
                4'b0001: ir <= 4'b0001; // IDCODE does not change on tms=1 in CAPTURE_IR
                4'b0010: ir <= 4'b0000; // Unsupported, go to reset state
                4'b0011: ir <= 4'b0000; // Unsupported, go to reset state
                default: ir <= 4'b0000; // Any other instruction goes to reset state
            endcase
        end else begin
            if (ir == 4'b0001) begin
...
functional details
[stdout]
ERROR: IDCODE readback failed. Expected A5, got 54
ERROR: initial DBG_CTL scan should have shifted out 00, got 2a
ERROR: DBG_CTL update failed. Expected 3C, got 00
ERROR: DBG_CTL readback failed. Expected 3C, got 2b
ERROR: DBG_CTL readback corrupted dbg_control.
ERROR: DBG_STAT readback failed. Expected 96, got 53
ERROR: DBG_STAT access unexpectedly modified dbg_control.
TEST_FAILED
/workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps)
synthesis details
[error]
None
errors[]
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 54",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}