Назад к моделям Назад к профилю модели

deepseek-coder-v2:16b | RAG off

06_reset_domain_crossing / task_60 | reset_sync_2ff

benchmarkilyasov
task_idilyasov/06_reset_domain_crossing/task_60
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260427_102437_171676_163c0c

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260427_102437_171676_163c0c ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260427_102437_171676_163c0c__sample_1
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

reg arst_meta1;
reg arst_meta2;

always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        arst_meta1 <= 0;
        arst_meta2 <= 0;
        srst_n     <= 0;
    end else begin
        arst_meta1 <= 1'b1;
        arst_meta2 <= arst_meta1;
        if (arst_meta2) begin
            srst_n <= 1'b1;
        end else begin
            srst_n <= 1'b0;
        end
    end
end

endmodule
functional details 
[stdout]
ERROR: local reset did not deassert after two clock edges.
ERROR: restart sequence failed to release reset after two edges.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260427_102437_171676_163c0c ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

reg arst_meta; // Meta-stable synchronization register for asynchronous reset
always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        arst_meta <= 0;
        srst_n <= 0;
    end else begin
        arst_meta <= 1;
        srst_n <= 0;
    end
end

reg [1:0] arst_sync; // Synchronization shift register for deassertion
always @(posedge clk) begin
    if (!arst_meta) begin
        arst_sync <= 2'b00;
    end else begin
        arst_sync <= {arst_sync[0], arst_meta};
        if (arst_sync == 2'b10) begin
            srst_n <= 1;
        end
    end
end

endmodule
functional details 
[stdout]
ERROR: local reset did not deassert after two clock edges.
ERROR: restart sequence failed to release reset after two edges.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260427_102437_171676_163c0c ok failed failed skipped failed syntax /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_3/generated.v:21: error: Could not find variable ``srand_n'' in ``reset_sync_2ff''
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

reg arst_d1;
reg arst_d2;

always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        arst_d1 <= 0;
        arst_d2 <= 0;
        srst_n <= 0;
    end else begin
        arst_d1 <= 1;
        arst_d2 <= arst_d1;
        if (arst_d2) begin
            srst_n <= 0;
        end else if (!arst_d2 && !arst_d1) begin
            srand_n <= 0;
        end else begin
            srand_n <= 1;
        end
    end
end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_3/generated.v:21: error: Could not find variable ``srand_n'' in ``reset_sync_2ff''
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_3/generated.v:23: error: Could not find variable ``srand_n'' in ``reset_sync_2ff''
2 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_3/functional/generated.v:21: error: Could not find variable ``srand_n'' in ``tb_task_60.dut''
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_3/functional/generated.v:23: error: Could not find variable ``srand_n'' in ``tb_task_60.dut''
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_3/generated.v:21: error: Could not find variable ``srand_n'' in ``reset_sync_2ff''\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_3/generated.v:23: error: Could not find variable ``srand_n'' in ``reset_sync_2ff''\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_3/functional/generated.v:21: error: Could not find variable ``srand_n'' in ``tb_task_60.dut''\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_3/functional/generated.v:23: error: Could not find variable ``srand_n'' in ``tb_task_60.dut''\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260427_102437_171676_163c0c ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

reg arst_meta; // metastable flip-flop for asynchronous reset
always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        arst_meta <= 0;
    end else begin
        arst_meta <= 1;
    end
end

reg arst_sync; // synchronized reset signal
always @(posedge clk or negedge arst_meta) begin
    if (!arst_meta) begin
        arst_sync <= 0;
    end else begin
        arst_sync <= arst_sync;
    end
end

reg [1:0] reset_cnt; // counter for deassertion sequence
always @(posedge clk or negedge arst_meta) begin
    if (!arst_meta) begin
        reset_cnt <= 2'b00;
    end else begin
        reset_cnt <= reset_cnt + 1'b1;
    end
end
...
functional details 
[stdout]
ERROR: local reset did not deassert after two clock edges.
ERROR: restart sequence failed to release reset after two edges.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260427_102437_171676_163c0c ok failed failed skipped failed syntax /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_5/generated.v:25: error: Could not find variable ``srand_n'' in ``reset_sync_2ff''
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260427_102437_171676_163c0c__sample_5
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

reg arst_meta; // metastable synchronization register for asynchronous reset
always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        arst_meta <= 0;
        srst_n <= 0;
    end else begin
        arst_meta <= 1;
    end
end

reg [1:0] reset_sync; // shift register for synchronous deassertion
always @(posedge clk) begin
    if (!arst_meta) begin
        reset_sync <= 2'b00;
        srst_n <= 0;
    end else begin
        reset_sync <= {reset_sync[0], arst_meta};
        if (reset_sync == 2'b11) begin
            srand_n <= 1;
        end else begin
            srand_n <= 0;
        end
    end
end

endmodule
syntax details 
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_5/generated.v:25: error: Could not find variable ``srand_n'' in ``reset_sync_2ff''
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_5/generated.v:27: error: Could not find variable ``srand_n'' in ``reset_sync_2ff''
2 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_5/functional/generated.v:25: error: Could not find variable ``srand_n'' in ``tb_task_60.dut''
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_5/functional/generated.v:27: error: Could not find variable ``srand_n'' in ``tb_task_60.dut''
2 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_5/generated.v:25: error: Could not find variable ``srand_n'' in ``reset_sync_2ff''\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_5/generated.v:27: error: Could not find variable ``srand_n'' in ``reset_sync_2ff''\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_5/functional/generated.v:25: error: Could not find variable ``srand_n'' in ``tb_task_60.dut''\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_5/functional/generated.v:27: error: Could not find variable ``srand_n'' in ``tb_task_60.dut''\n2 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260427_102437_171676_163c0c ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset was not asserted immediately.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

reg arst_meta; // metastable flip-flop for asynchronous reset
always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        arst_meta <= 0;
    end else begin
        arst_meta <= 1;
    end
end

reg srst_meta; // metastable flip-flop for synchronous reset
always @(posedge clk or negedge arst_meta) begin
    if (!arst_meta) begin
        srst_meta <= 0;
    end else begin
        srst_meta <= 1;
    end
end

reg [1:0] counter; // counter to track the number of clock cycles after arst_n goes high
always @(posedge clk or negedge srst_meta) begin
    if (!srst_meta) begin
        counter <= 2'b00;
    end else begin
        counter <= counter + 1;
    end
end
...
functional details 
[stdout]
ERROR: reset was not asserted immediately.
ERROR: local reset did not deassert after two clock edges.
ERROR: restart sequence failed to release reset after two edges.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset was not asserted immediately.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260427_102437_171676_163c0c ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

reg arst_meta; // Meta-stable synchronization register for asynchronous reset
always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        arst_meta <= 0;
        srst_n <= 0;
    end else begin
        arst_meta <= 1;
    end
end

reg [1:0] reset_sync; // Synchronization shift register for deassertion
always @(posedge clk or negedge arst_meta) begin
    if (!arst_meta) begin
        reset_sync <= 2'b00;
    end else begin
        reset_sync <= {reset_sync[0], 1'b1};
    end
end

always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        srst_n <= 0;
    end else if (reset_sync == 2'b11) begin
        srst_n <= 1;
    end
end
...
functional details 
[stdout]
ERROR: local reset did not deassert after two clock edges.
ERROR: restart sequence failed to release reset after two edges.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260427_102437_171676_163c0c ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

reg arst_meta; // metastable synchronization register for asynchronous reset
always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        arst_meta <= 1'b0;
    end else begin
        arst_meta <= 1'b1;
    end
end

reg srst_meta; // metastable synchronization register for synchronous reset
always @(posedge clk or negedge arst_meta) begin
    if (!arst_meta) begin
        srst_meta <= 1'b0;
    end else begin
        srst_meta <= 1'b1;
    end
end

reg [1:0] deassert_cnt; // counter to count the number of clock cycles after arst_n returns to 1
always @(posedge clk) begin
    if (!arst_meta) begin
        deassert_cnt <= 2'b00;
    end else if (deassert_cnt != 2'b11) begin
        deassert_cnt <= deassert_cnt + 1'b1;
    end
end
...
functional details 
[stdout]
ERROR: local reset did not deassert after two clock edges.
ERROR: restart sequence failed to release reset after two edges.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260427_102437_171676_163c0c ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

reg arst_meta; // metastable flip-flop for asynchronous reset
always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        arst_meta <= 0;
    end else begin
        arst_meta <= 1;
    end
end

reg arst_sync; // synchronized reset signal
always @(posedge clk or negedge arst_meta) begin
    if (!arst_meta) begin
        arst_sync <= 0;
    end else begin
        arst_sync <= arst_sync;
    end
end

reg [1:0] arst_cnt; // counter for deassertion sequence
always @(posedge clk or negedge arst_meta) begin
    if (!arst_meta) begin
        arst_cnt <= 2'b00;
    end else begin
        arst_cnt <= arst_cnt + 1'b1;
    end
end
...
functional details 
[stdout]
ERROR: local reset deasserted after only one clock edge.
ERROR: restart sequence released reset too early after one edge.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset deasserted after only one clock edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260427_102437_171676_163c0c ok failed failed skipped failed syntax /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_10/generated.v:31: error: Could not find variable ``srand_n'' in ``reset_sync_2ff''
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output reg srst_n
);

reg arst_meta; // metastable synchronization register for asynchronous reset
always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        arst_meta <= 0;
        srst_n <= 0;
    end else begin
        arst_meta <= 1;
        srst_n <= 0;
    end
end

reg [1:0] arst_sync; // synchronization shift register for asynchronous reset
always @(posedge clk or negedge arst_meta) begin
    if (!arst_meta) begin
        arst_sync <= 2'b00;
    end else begin
        arst_sync <= {arst_sync[0], 1'b1};
    end
end

always @(posedge clk) begin
    if (arst_sync == 2'b11) begin
        srst_n <= 1;
    end else if (!arst_n) begin
        srand_n <= 0;
    end
...
syntax details 
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_10/generated.v:31: error: Could not find variable ``srand_n'' in ``reset_sync_2ff''
1 error(s) during elaboration.
functional details 
[stderr]
/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_10/functional/generated.v:31: error: Could not find variable ``srand_n'' in ``tb_task_60.dut''
1 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_10/generated.v:31: error: Could not find variable ``srand_n'' in ``reset_sync_2ff''\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__06_reset_domain_crossing__task_60/sample_10/functional/generated.v:31: error: Could not find variable ``srand_n'' in ``tb_task_60.dut''\n1 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}