07_csr_register_map_generation / task_71 | apb_lock_cfg
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260427_102437_171676_163c0c__sample_1
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output reg pready,
input hw_fault_evt,
output reg [1:0] mode,
output reg [7:0] limit,
output reg cfg_locked,
output reg fault_sticky,
output reg apply_pulse
);
reg [31:0] cfg;
reg [31:0] lock;
reg [31:0] status;
reg [31:0] cmd;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cfg <= 32'h0;
lock <= 32'h0;
status <= 32'h0;
cmd <= 32'h0;
mode <= 2'b0;
limit <= 8'h0;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: CFG partial writes failed. ERROR: lock bit failed to set. ERROR: CFG changed even though cfg_locked was asserted. ERROR: hw_fault_evt did not set fault_sticky. ERROR: writing 0 incorrectly cleared fault_sticky. ERROR: apply_pulse did not assert. ERROR: LOCK register readback failed. Got 00000000 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output reg pready,
input hw_fault_evt,
output reg [1:0] mode,
output reg [7:0] limit,
output reg cfg_locked,
output reg fault_sticky,
output reg apply_pulse
);
reg [31:0] cfg;
reg [31:0] lock;
reg [31:0] status;
reg [31:0] cmd;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cfg <= 32'h0;
lock <= 32'h0;
status <= 32'h0;
cmd <= 32'h0;
mode <= 2'b0;
limit <= 8'h0;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: CFG partial writes failed. ERROR: lock bit failed to set. ERROR: CFG changed even though cfg_locked was asserted. ERROR: writing 0 incorrectly cleared fault_sticky. ERROR: W1C clear of fault_sticky failed. ERROR: apply_pulse lasted longer than one cycle. TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output reg pready,
input hw_fault_evt,
output reg [1:0] mode,
output reg [7:0] limit,
output reg cfg_locked,
output reg fault_sticky,
output reg apply_pulse
);
reg [31:0] cfg;
reg [31:0] lock;
reg [31:0] status;
reg [31:0] cmd;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cfg <= 32'b0;
lock <= 32'b0;
status <= 32'b0;
cmd <= 32'b0;
pready <= 1'b0;
end else if (psel && penable) begin
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: CFG partial writes failed. ERROR: lock bit failed to set. ERROR: CFG changed even though cfg_locked was asserted. ERROR: W1C clear of fault_sticky failed. ERROR: apply_pulse did not assert. ERROR: LOCK register readback failed. Got 00000000 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output reg pready,
input hw_fault_evt,
output reg [1:0] mode,
output reg [7:0] limit,
output reg cfg_locked,
output reg fault_sticky,
output reg apply_pulse
);
reg [31:0] cfg;
reg [31:0] lock;
reg [31:0] status;
reg [31:0] cmd;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cfg <= 32'h0;
lock <= 32'h0;
status <= 32'h0;
cmd <= 32'h0;
mode <= 2'b0;
limit <= 8'h0;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: CFG partial writes failed. ERROR: lock bit failed to set. ERROR: CFG changed even though cfg_locked was asserted. ERROR: hw_fault_evt did not set fault_sticky. ERROR: writing 0 incorrectly cleared fault_sticky. ERROR: apply_pulse did not assert. ERROR: LOCK register readback failed. Got 00000000 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260427_102437_171676_163c0c__sample_5
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output reg pready,
input hw_fault_evt,
output reg [1:0] mode,
output reg [7:0] limit,
output reg cfg_locked,
output reg fault_sticky,
output reg apply_pulse
);
reg [31:0] cfg;
reg [31:0] lock;
reg [31:0] status;
reg [31:0] cmd;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cfg <= 32'h0;
lock <= 32'h0;
status <= 32'h0;
cmd <= 32'h0;
mode <= 2'b0;
limit <= 8'h0;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: CFG partial writes failed. ERROR: lock bit failed to set. ERROR: CFG changed even though cfg_locked was asserted. ERROR: hw_fault_evt did not set fault_sticky. ERROR: writing 0 incorrectly cleared fault_sticky. ERROR: apply_pulse did not assert. ERROR: LOCK register readback failed. Got 00000002 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output reg pready,
input hw_fault_evt,
output reg [1:0] mode,
output reg [7:0] limit,
output reg cfg_locked,
output reg fault_sticky,
output reg apply_pulse
);
reg [31:0] cfg;
reg [31:0] lock;
reg [31:0] status;
reg [31:0] cmd;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cfg <= 32'h0;
lock <= 32'h0;
status <= 32'h0;
cmd <= 32'h0;
mode <= 2'b0;
limit <= 8'h0;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: CFG partial writes failed. ERROR: lock bit failed to set. ERROR: CFG changed even though cfg_locked was asserted. ERROR: W1C clear of fault_sticky failed. ERROR: apply_pulse did not assert. ERROR: LOCK register readback failed. Got 00000002 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output reg pready,
input hw_fault_evt,
output reg [1:0] mode,
output reg [7:0] limit,
output reg cfg_locked,
output reg fault_sticky,
output reg apply_pulse
);
reg [31:0] cfg;
reg [31:0] lock;
reg [31:0] status;
reg [31:0] cmd;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cfg <= 32'h0;
lock <= 32'h0;
status <= 32'h0;
cmd <= 32'h0;
mode <= 2'b0;
limit <= 8'h0;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: CFG partial writes failed. ERROR: lock bit failed to set. ERROR: CFG changed even though cfg_locked was asserted. ERROR: hw_fault_evt did not set fault_sticky. ERROR: writing 0 incorrectly cleared fault_sticky. ERROR: apply_pulse did not assert. ERROR: LOCK register readback failed. Got 00000c02 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output reg pready,
input hw_fault_evt,
output reg [1:0] mode,
output reg [7:0] limit,
output reg cfg_locked,
output reg fault_sticky,
output reg apply_pulse
);
reg [31:0] cfg;
reg [31:0] lock;
reg [31:0] status;
reg [31:0] cmd;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cfg <= 32'h0;
lock <= 32'h0;
status <= 32'h0;
cmd <= 32'h0;
mode <= 2'b0;
limit <= 8'h0;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: CFG partial writes failed. ERROR: lock bit failed to set. ERROR: CFG changed even though cfg_locked was asserted. ERROR: W1C clear of fault_sticky failed. ERROR: apply_pulse did not assert. ERROR: LOCK register readback failed. Got 00000002 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output reg pready,
input hw_fault_evt,
output reg [1:0] mode,
output reg [7:0] limit,
output reg cfg_locked,
output reg fault_sticky,
output reg apply_pulse
);
reg [31:0] cfg;
reg [31:0] lock;
reg [31:0] status;
reg [31:0] cmd;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cfg <= 32'h0;
lock <= 32'h0;
status <= 32'h0;
cmd <= 32'h0;
mode <= 2'b0;
limit <= 8'h0;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: CFG partial writes failed. ERROR: lock bit failed to set. ERROR: CFG changed even though cfg_locked was asserted. ERROR: hw_fault_evt did not set fault_sticky. ERROR: writing 0 incorrectly cleared fault_sticky. ERROR: apply_pulse did not assert. ERROR: LOCK register readback failed. Got 00000000 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output reg pready,
input hw_fault_evt,
output reg [1:0] mode,
output reg [7:0] limit,
output reg cfg_locked,
output reg fault_sticky,
output reg apply_pulse
);
reg [31:0] cfg;
reg [31:0] lock;
reg [31:0] status;
reg [31:0] cmd;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
cfg <= 32'h0;
lock <= 32'h0;
status <= 32'h0;
cmd <= 32'h0;
mode <= 2'b0;
limit <= 8'h0;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: CFG partial writes failed. ERROR: CFG changed even though cfg_locked was asserted. ERROR: hw_fault_evt did not set fault_sticky. ERROR: writing 0 incorrectly cleared fault_sticky. ERROR: LOCK register readback failed. Got 00000000 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|