07_csr_register_map_generation / task_72 | axil_sensor_csr
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_1
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output reg awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output reg wready,
output reg [1:0] bresp,
output reg bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output reg arready,
output reg [31:0] rdata,
output reg [1:0] rresp,
output reg rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output reg block_enable,
output reg [7:0] gain,
output reg kick_pulse,
output reg irq_sticky
);
// Register addresses
localparam CTRL = 8'h00;
localparam STATUS = 8'h04;
localparam CMD = 8'h08;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: irq_evt did not set irq_sticky. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000001 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: writing 0 incorrectly cleared irq_sticky. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: kick_pulse did not assert on CMD write. ERROR: kick_pulse lasted longer than one cycle. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: CMD register should read as zero. Got 00000001 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output reg awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output reg wready,
output reg [1:0] bresp,
output reg bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output reg arready,
output reg [31:0] rdata,
output reg [1:0] rresp,
output reg rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output reg block_enable,
output reg [7:0] gain,
output reg kick_pulse,
output reg irq_sticky
);
// Register addresses
localparam CTRL = 8'h00;
localparam STATUS = 8'h04;
localparam CMD = 8'h08;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00008001 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: kick_pulse did not assert on CMD write. ERROR: kick_pulse lasted longer than one cycle. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: CMD register should read as zero. Got 00000001 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output reg awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output reg wready,
output reg [1:0] bresp,
output reg bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output reg arready,
output reg [31:0] rdata,
output reg [1:0] rresp,
output reg rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output reg block_enable,
output reg [7:0] gain,
output reg kick_pulse,
output reg irq_sticky
);
// Register addresses
localparam CTRL = 8'h00;
localparam STATUS = 8'h04;
localparam CMD = 8'h08;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL gain field failed. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: irq_evt did not set irq_sticky. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000001 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: writing 0 incorrectly cleared irq_sticky. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: AXI-Lite CMD write response was not generated correctly. ERROR: kick_pulse did not assert on CMD write. ERROR: kick_pulse lasted longer than one cycle. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: CMD register should read as zero. Got 00000001 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output reg awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output reg wready,
output reg [1:0] bresp,
output reg bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output reg arready,
output reg [31:0] rdata,
output reg [1:0] rresp,
output reg rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output reg block_enable,
output reg [7:0] gain,
output reg kick_pulse,
output reg irq_sticky
);
// Register addresses
localparam CTRL = 8'h00;
localparam STATUS = 8'h04;
localparam CMD = 8'h08;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL gain field failed. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: irq_evt did not set irq_sticky. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000001 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: writing 0 incorrectly cleared irq_sticky. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: kick_pulse did not assert on CMD write. ERROR: kick_pulse lasted longer than one cycle. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: CMD register should read as zero. Got 00000001 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_102437_171676_163c0c | ok | failed | failed | skipped | failed | syntax | _07_csr_register_map_generation__task_72/sample_5/generated.v:63: Syntax in assignment statement l-value. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_5
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output reg awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output reg wready,
output reg [1:0] bresp,
output reg bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output reg arready,
output reg [31:0] rdata,
output reg [1:0] rresp,
output reg rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output reg block_enable,
output reg [7:0] gain,
output reg kick_pulse,
output reg irq_sticky
);
// Register addresses
localparam CTRL = 8'h00;
localparam STATUS = 8'h04;
localparam CMD = 8'h08;
...
syntax details[stderr] _07_csr_register_map_generation__task_72/sample_5/generated.v:63: Syntax in assignment statement l-value. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:64: syntax error /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:64: Syntax in assignment statement l-value. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:65: syntax error /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:70: Syntax in assignment statement l-value. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:70: syntax error /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:70: error: Malformed statement /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:70: syntax error /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:73: Syntax in assignment statement l-value. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:74: syntax error /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:80: Syntax in assignment statement l-value. /data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:118: syntax error I give up. functional details[stderr] Incomprehensible case expression. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:21: syntax error /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:21: error: Malformed statement /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:21: error: Incomprehensible case expression. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:22: syntax error /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:24: error: Malformed statement /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:24: error: Incomprehensible case expression. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:25: syntax error /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:28: error: Malformed statement /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:28: error: Incomprehensible case expression. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:29: syntax error /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:32: error: Malformed statement /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:32: error: Incomprehensible case expression. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:33: syntax error /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:64: error: Malformed statement /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:64: error: Incomprehensible case expression. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:65: syntax error /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:65: error: Malformed statement /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:65: error: Incomprehensible case expression. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:66: syntax error /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:66: error: Malformed statement /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:66: error: Incomprehensible case expression. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:67: syntax error /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:98: error: Malformed statement /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:98: error: Incomprehensible case expression. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:99: syntax error /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:99: error: Malformed statement /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:99: error: Incomprehensible case expression. /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:100: syntax error /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:129: error: Malformed statement /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:129: error: Incomprehensible case expression. ... synthesis details[error] None errors[][
{
"stage": "syntax",
"code": "syntax.iverilog_failed",
"message": "_07_csr_register_map_generation__task_72/sample_5/generated.v:63: Syntax in assignment statement l-value.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:64: syntax error\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:64: Syntax in assignment statement l-value.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:65: syntax error\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:70: Syntax in assignment statement l-value.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:70: syntax error\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:70: error: Malformed statement\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:70: syntax error\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:73: Syntax in assignment statement l-value.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:74: syntax error\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:80: Syntax in assignment statement l-value.\n/data/eval/out/run_20260427_102437_171676_163c0c/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_5/generated.v:118: syntax error\nI give up.\n",
"retryable": false,
"details": {}
},
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "Incomprehensible case expression.\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:21: syntax error\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:21: error: Malformed statement\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:21: error: Incomprehensible case expression.\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:22: syntax error\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:24: error: Malformed statement\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:24: error: Incomprehensible case expression.\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:25: syntax error\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:28: error: Malformed statement\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:28: error: Incomprehensible case expression.\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:29: syntax error\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:32: error: Malformed statement\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:32: error: Incomprehensible case expression.\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:33: syntax error\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:64: error: Malformed statement\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:64: error: Incomprehensible case expression.\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:65: syntax error\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:65: error: Malformed statement\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:65: error: Incomprehensible case expression.\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:66: syntax error\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:66: error: Malformed statement\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:66: error: Incomprehensible case expression.\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:67: syntax error\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:98: error: Malformed statement\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:98: error: Incomprehensible case expression.\n/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:99: syntax error\n/workspace/banchmarks/pashencev/07_csr_reg…
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output reg awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output reg wready,
output reg [1:0] bresp,
output reg bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output reg arready,
output reg [31:0] rdata,
output reg [1:0] rresp,
output reg rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output reg block_enable,
output reg [7:0] gain,
output reg kick_pulse,
output reg irq_sticky
);
// Register addresses
localparam CTRL = 8'h00;
localparam STATUS = 8'h04;
localparam CMD = 8'h08;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL gain field failed. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: irq_evt did not set irq_sticky. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000001 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: writing 0 incorrectly cleared irq_sticky. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: kick_pulse did not assert on CMD write. ERROR: AXI-Lite read channel was not ready in idle state. TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output reg awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output reg wready,
output reg [1:0] bresp,
output reg bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output reg arready,
output reg [31:0] rdata,
output reg [1:0] rresp,
output reg rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output reg block_enable,
output reg [7:0] gain,
output reg kick_pulse,
output reg irq_sticky
);
// Register addresses
localparam CTRL = 8'h00;
localparam STATUS = 8'h04;
localparam CMD = 8'h08;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000000 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: writing 0 incorrectly cleared irq_sticky. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: AXI-Lite CMD write response was not generated correctly. ERROR: kick_pulse did not assert on CMD write. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: CMD register should read as zero. Got 00000001 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output reg awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output reg wready,
output reg [1:0] bresp,
output reg bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output reg arready,
output reg [31:0] rdata,
output reg [1:0] rresp,
output reg rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output reg block_enable,
output reg [7:0] gain,
output reg kick_pulse,
output reg irq_sticky
);
// Register addresses
localparam CTRL = 8'h00;
localparam STATUS = 8'h04;
localparam CMD = 8'h08;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL gain field failed. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: irq_evt did not set irq_sticky. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000001 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: writing 0 incorrectly cleared irq_sticky. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: kick_pulse did not assert on CMD write. ERROR: kick_pulse lasted longer than one cycle. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: CMD register should read as zero. Got 00000001 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output reg awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output reg wready,
output reg [1:0] bresp,
output reg bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output reg arready,
output reg [31:0] rdata,
output reg [1:0] rresp,
output reg rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output reg block_enable,
output reg [7:0] gain,
output reg kick_pulse,
output reg irq_sticky
);
// Register addresses
localparam CTRL = 8'h00;
localparam STATUS = 8'h04;
localparam CMD = 8'h08;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: byte-lane write to CTRL gain field failed. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: irq_evt did not set irq_sticky. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000000 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: writing 0 incorrectly cleared irq_sticky. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: AXI-Lite write response was not generated correctly. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: AXI-Lite CMD write response was not generated correctly. ERROR: kick_pulse did not assert on CMD write. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: AXI-Lite read response was not generated correctly. ERROR: CMD register should read as zero. Got 00000001 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260427_102437_171676_163c0c | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v previewmodule axil_sensor_csr (
input clk,
input rst_n,
input [7:0] awaddr,
input awvalid,
output reg awready,
input [31:0] wdata,
input [3:0] wstrb,
input wvalid,
output reg wready,
output reg [1:0] bresp,
output reg bvalid,
input bready,
input [7:0] araddr,
input arvalid,
output reg arready,
output reg [31:0] rdata,
output reg [1:0] rresp,
output reg rvalid,
input rready,
input [7:0] hw_level,
input irq_evt,
output reg block_enable,
output reg [7:0] gain,
output reg kick_pulse,
output reg irq_sticky
);
// Register addresses
localparam CTRL = 8'h00;
localparam STATUS = 8'h04;
localparam CMD = 8'h08;
...
functional details[stdout] ERROR: reset values are incorrect. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL bit 0 failed. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: byte-lane write to CTRL gain field failed. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000 ERROR: irq_evt did not set irq_sticky. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000001 ERROR: AXI-Lite write channel was not ready in idle state. ERROR: writing 0 incorrectly cleared irq_sticky. ERROR: AXI-Lite write channel was not ready in idle state. ERROR: W1C clear of irq_sticky failed. ERROR: AXI-Lite write channel was not ready for CMD write. ERROR: kick_pulse did not assert on CMD write. ERROR: kick_pulse lasted longer than one cycle. ERROR: AXI-Lite read channel was not ready in idle state. ERROR: CMD register should read as zero. Got 00000001 TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|