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deepseek-coder-v2:16b | RAG off

13_rtllm_arithmetic / task_06 | verified_adder_64bit

benchmarkrtllm
task_idrtllm/13_rtllm_arithmetic/task_06
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260427_102437_171676_163c0c

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_1
generated.v preview 
module adder_pipe_64bit (
    input wire clk,
    input wire rst_n,
    input wire i_en,
    input wire [63:0] adda,
    input wire [63:0] addb,
    output reg [64:0] result,
    output reg o_en
);

reg [64:0] stage1;
reg [64:0] stage2;
reg [64:0] stage3;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end else if (i_en) begin
        stage1 <= {1'b0, adda} + {1'b0, addb};
        stage2 <= stage1;
        stage3 <= stage2;
        o_en <= 1'b1;
    end else begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end
end
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v preview 
module adder_pipe_64bit (
    input wire clk,
    input wire rst_n,
    input wire i_en,
    input wire [63:0] adda,
    input wire [63:0] addb,
    output reg [64:0] result,
    output reg o_en
);

reg [64:0] stage1;
reg [64:0] stage2;
reg [64:0] stage3;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end else if (i_en) begin
        stage1 <= {1'b0, adda} + {1'b0, addb};
        stage2 <= stage1;
        stage3 <= stage2;
        o_en <= 1'b1;
    end else begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end
end
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v preview 
module adder_pipe_64bit (
    input wire clk,
    input wire rst_n,
    input wire i_en,
    input wire [63:0] adda,
    input wire [63:0] addb,
    output reg [64:0] result,
    output reg o_en
);

reg [64:0] stage1;
reg [64:0] stage2;
reg [64:0] stage3;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end else if (i_en) begin
        stage1 <= {1'b0, adda} + {1'b0, addb};
        stage2 <= stage1;
        stage3 <= stage2;
        o_en <= 1'b1;
    end else begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end
end
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v preview 
module adder_pipe_64bit (
    input wire clk,
    input wire rst_n,
    input wire i_en,
    input wire [63:0] adda,
    input wire [63:0] addb,
    output reg [64:0] result,
    output reg o_en
);

reg [64:0] stage1;
reg [64:0] stage2;
reg [64:0] stage3;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end else if (i_en) begin
        stage1 <= {1'b0, adda} + {1'b0, addb}; // Addition with carry input set to 0
        stage2 <= stage1;
        stage3 <= stage2;
        o_en <= 1'b1;
    end else begin
        o_en <= 1'b0;
    end
end

always @(*) begin
    result = stage3;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_5
generated.v preview 
module adder_pipe_64bit (
    input wire clk,
    input wire rst_n,
    input wire i_en,
    input wire [63:0] adda,
    input wire [63:0] addb,
    output reg [64:0] result,
    output reg o_en
);

reg [64:0] stage1;
reg [64:0] stage2;
reg [64:0] stage3;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end else if (i_en) begin
        stage1 <= {1'b0, adda} + {1'b0, addb};
        stage2 <= stage1;
        stage3 <= stage2;
        o_en <= 1'b1;
    end else begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end
end
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v preview 
module adder_pipe_64bit (
    input wire clk,
    input wire rst_n,
    input wire i_en,
    input wire [63:0] adda,
    input wire [63:0] addb,
    output reg [64:0] result,
    output reg o_en
);

reg [63:0] stage1;
reg [63:0] stage2;
reg [63:0] stage3;
reg [63:0] stage4;
reg [63:0] stage5;
reg [63:0] stage6;
reg [63:0] stage7;
reg [63:0] stage8;
reg [63:0] stage9;
reg [63:0] stage10;
reg [63:0] stage11;
reg [63:0] stage12;
reg [63:0] stage13;
reg [63:0] stage14;
reg [63:0] stage15;
reg [63:0] stage16;
reg [63:0] stage17;
reg [63:0] stage18;
reg [63:0] stage19;
reg [63:0] stage20;
reg [63:0] stage21;
reg [63:0] stage22;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v preview 
module adder_pipe_64bit (
    input wire clk,
    input wire rst_n,
    input wire i_en,
    input wire [63:0] adda,
    input wire [63:0] addb,
    output reg [64:0] result,
    output reg o_en
);

reg [64:0] stage1;
reg [64:0] stage2;
reg [64:0] stage3;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end else if (i_en) begin
        stage1 <= {1'b0, adda} + {1'b0, addb}; // Addition with carry input initialized to 0
        stage2 <= stage1;
        stage3 <= stage2;
        o_en <= 1'b1;
    end else begin
        o_en <= 1'b0;
    end
end

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v preview 
module adder_pipe_64bit (
    input wire clk,
    input wire rst_n,
    input wire i_en,
    input wire [63:0] adda,
    input wire [63:0] addb,
    output reg [64:0] result,
    output reg o_en
);

reg [64:0] stage1;
reg [64:0] stage2;
reg [64:0] stage3;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end else if (i_en) begin
        stage1 <= {1'b0, adda} + {1'b0, addb}; // Addition with carry input set to 0
        stage2 <= stage1;
        stage3 <= stage2;
        o_en <= 1'b1;
    end else begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end
end
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v preview 
module adder_pipe_64bit (
    input wire clk,
    input wire rst_n,
    input wire i_en,
    input wire [63:0] adda,
    input wire [63:0] addb,
    output reg [64:0] result,
    output reg o_en
);

reg [64:0] stage1;
reg [64:0] stage2;
reg [64:0] stage3;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end else if (i_en) begin
        stage1 <= {1'b0, adda} + {1'b0, addb};
        stage2 <= stage1;
        stage3 <= stage2;
        o_en <= 1'b1;
    end else begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end
end
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v preview 
module adder_pipe_64bit (
    input wire clk,
    input wire rst_n,
    input wire i_en,
    input wire [63:0] adda,
    input wire [63:0] addb,
    output reg [64:0] result,
    output reg o_en
);

reg [64:0] stage1;
reg [64:0] stage2;
reg [64:0] stage3;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        stage1 <= 65'b0;
        stage2 <= 65'b0;
        stage3 <= 65'b0;
        o_en <= 1'b0;
    end else if (i_en) begin
        stage1 <= {1'b0, adda} + {1'b0, addb}; // Addition with carry input set to 0
        stage2 <= stage1;
        stage3 <= stage2;
        o_en <= 1'b1;
    end else begin
        o_en <= 1'b0;
    end
end

always @(*) begin
    result = stage3;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}