13_rtllm_arithmetic / task_10 | verified_radix2_div
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260427_102437_171676_163c0c | failed | failed | failed | skipped | failed | extract | Model response is empty |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_102437_171676_163c0c__sample_1
synthesis details[error] None errors[][
{
"stage": "model_request",
"code": "model_request.failed",
"message": "HTTPConnectionPool(host='ollama', port=11434): Read timed out. (read timeout=120)",
"retryable": true,
"details": {}
},
{
"stage": "extract",
"code": "extract.no_verilog_found",
"message": "Model response is empty",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": false,
"extract_ok": false,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260427_102437_171676_163c0c | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v previewmodule radix2_div (
input wire clk,
input wire rst,
input wire sign,
input wire [7:0] dividend,
input wire [7:0] divisor,
input wire opn_valid,
input wire res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] sr;
reg [2:0] cnt;
reg start_cnt;
reg NEG_DIVISOR;
reg [7:0] temp_dividend;
reg [7:0] temp_divisor;
always @(posedge clk or posedge rst) begin
if (rst) begin
sr <= 16'b0;
cnt <= 3'b0;
start_cnt <= 1'b0;
res_valid <= 1'b0;
end else if (opn_valid && !res_valid) begin
abs_dividend = (dividend[7] & sign) ? -dividend : dividend;
abs_divisor = (divisor[7] & sign) ? -divisor : divisor;
sr <= {abs_dividend, 1'b0};
NEG_DIVISOR <= -abs_divisor;
...
functional details[stdout] Error: dividend=100, divisor= 10, expected=000a, got=0000 Error: dividend=156, divisor= 10, expected=00f6, got=6400 Error: dividend=100, divisor=246, expected=00f6, got=6400 Error: dividend=156, divisor=246, expected=000a, got=6400 Error: dividend=123, divisor=123, expected=0001, got=6400 Error: dividend= 0, divisor=123, expected=0000, got=7a00 Error: dividend=123, divisor=251, expected=7b00, got=ff00 Error: dividend=255, divisor= 7, expected=0324, got=7a00 ===========Failed=========== 8 /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 825000 (1ps) synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_102437_171676_163c0c | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v previewmodule radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] sr;
reg [3:0] cnt;
reg start_cnt;
reg NEG_DIVISOR;
reg [15:0] temp_result;
always @(posedge clk or posedge rst) begin
if (rst) begin
res_valid <= 0;
sr <= 0;
cnt <= 0;
start_cnt <= 0;
NEG_DIVISOR <= 0;
end else if (opn_valid && !res_valid) begin
abs_dividend <= (dividend[7] ? -dividend : dividend);
abs_divisor <= (divisor[7] ? -divisor : divisor);
sr <= {abs_dividend, 1'b0};
NEG_DIVISOR <= -abs_divisor;
...
functional details[stdout] Error: dividend=100, divisor= 10, expected=000a, got=0008 Error: dividend=156, divisor= 10, expected=00f6, got=0008 Error: dividend=100, divisor=246, expected=00f6, got=0008 Error: dividend=156, divisor=246, expected=000a, got=0008 Error: dividend=123, divisor=123, expected=0001, got=0008 Error: dividend= 0, divisor=123, expected=0000, got=0008 Error: dividend=123, divisor=251, expected=7b00, got=0008 Error: dividend=255, divisor= 7, expected=0324, got=0008 ===========Failed=========== 8 /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 825000 (1ps) synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_102437_171676_163c0c | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v previewmodule radix2_div (
input wire clk,
input wire rst,
input wire sign,
input wire [7:0] dividend,
input wire [7:0] divisor,
input wire opn_valid,
input wire res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] sr;
reg [3:0] cnt;
reg start_cnt;
reg neg_divisor;
reg [15:0] NEG_DIVISOR;
always @(posedge clk or posedge rst) begin
if (rst) begin
res_valid <= 0;
sr <= 0;
cnt <= 0;
start_cnt <= 0;
neg_divisor <= 0;
end else if (opn_valid && !res_valid) begin
abs_dividend = dividend[7] ? -dividend : dividend;
abs_divisor = divisor[7] ? -divisor : divisor;
sr = {abs_dividend, 1'b0};
neg_divisor <= divisor[7];
...
functional details[stdout] Error: dividend=100, divisor= 10, expected=000a, got=00d2 Error: dividend=156, divisor= 10, expected=00f6, got=00d2 Error: dividend=100, divisor=246, expected=00f6, got=00d2 Error: dividend=156, divisor=246, expected=000a, got=00d2 Error: dividend=123, divisor=123, expected=0001, got=00d2 Error: dividend= 0, divisor=123, expected=0000, got=00d2 Error: dividend=123, divisor=251, expected=7b00, got=00d2 Error: dividend=255, divisor= 7, expected=0324, got=00d2 ===========Failed=========== 8 /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 335000 (1ps) synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_102437_171676_163c0c | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_102437_171676_163c0c__sample_5
generated.v previewmodule radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg neg_divisor;
reg [15:0] sr;
reg start_cnt;
reg [3:0] cnt;
wire [15:0] neg_sr;
assign neg_sr = ~sr + 1;
always @(posedge clk or posedge rst) begin
if (rst) begin
res_valid <= 0;
start_cnt <= 0;
cnt <= 0;
end else if (opn_valid && !res_valid) begin
abs_dividend <= sign ? -dividend : dividend;
abs_divisor <= sign ? -divisor : divisor;
neg_divisor <= sign ? 1'b1 : 1'b0;
sr <= {abs_dividend, 1'b0};
start_cnt <= 1;
...
functional details[stdout] Error: dividend=100, divisor= 10, expected=000a, got=0000 Error: dividend=156, divisor= 10, expected=00f6, got=00c8 Error: dividend=100, divisor=246, expected=00f6, got=00c8 Error: dividend=156, divisor=246, expected=000a, got=0138 Error: dividend=123, divisor=123, expected=0001, got=00c8 Error: dividend= 0, divisor=123, expected=0000, got=00f6 Error: dividend=123, divisor=251, expected=7b00, got=0000 Error: dividend=255, divisor= 7, expected=0324, got=00f6 ===========Failed=========== 8 /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 825000 (1ps) synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260427_102437_171676_163c0c | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v previewmodule radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] sr;
reg [2:0] cnt;
reg start_cnt;
reg NEG_DIVISOR;
reg [15:0] temp_result;
always @(posedge clk or posedge rst) begin
if (rst) begin
res_valid <= 0;
sr <= 0;
cnt <= 0;
start_cnt <= 0;
NEG_DIVISOR <= 0;
end else if (opn_valid && !res_valid) begin
abs_dividend <= (dividend[7] ? -dividend : dividend);
abs_divisor <= (divisor[7] ? -divisor : divisor);
sr <= {abs_dividend, 1'b0};
NEG_DIVISOR <= -abs_divisor;
...
functional details[stdout] Error: dividend=100, divisor= 10, expected=000a, got=xxX0 Error: dividend=156, divisor= 10, expected=00f6, got=xxX0 Error: dividend=100, divisor=246, expected=00f6, got=xxX0 Error: dividend=156, divisor=246, expected=000a, got=xxX0 Error: dividend=123, divisor=123, expected=0001, got=xxX0 Error: dividend= 0, divisor=123, expected=0000, got=xxX0 Error: dividend=123, divisor=251, expected=7b00, got=xxX0 Error: dividend=255, divisor= 7, expected=0324, got=xxX0 ===========Failed=========== 8 /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 325000 (1ps) synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_102437_171676_163c0c | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v previewmodule radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] sr;
reg [3:0] cnt;
reg start_cnt;
reg NEG_DIVISOR;
reg [15:0] temp_result;
always @(posedge clk or posedge rst) begin
if (rst) begin
res_valid <= 0;
sr <= 0;
cnt <= 0;
start_cnt <= 0;
NEG_DIVISOR <= 0;
end else if (opn_valid && !res_valid) begin
abs_dividend <= sign ? -dividend : dividend;
abs_divisor <= sign ? -divisor : divisor;
sr <= {abs_dividend, 1'b0};
NEG_DIVISOR <= -abs_divisor;
...
functional details[stdout] Error: dividend=100, divisor= 10, expected=000a, got=xxXx Error: dividend=156, divisor= 10, expected=00f6, got=9200 Error: dividend=100, divisor=246, expected=00f6, got=01fc Error: dividend=156, divisor=246, expected=000a, got=01fb Error: dividend=123, divisor=123, expected=0001, got=e900 Error: dividend=123, divisor=251, expected=7b00, got=0500 Error: dividend=255, divisor= 7, expected=0324, got=fc08 ===========Failed=========== 7 /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 825000 (1ps) synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260427_102437_171676_163c0c | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v previewmodule radix2_div (
input wire clk,
input wire rst,
input wire sign,
input wire [7:0] dividend,
input wire [7:0] divisor,
input wire opn_valid,
input wire res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] sr;
reg [2:0] cnt;
reg start_cnt;
reg NEG_DIVISOR;
reg [15:0] temp_result;
always @(posedge clk or posedge rst) begin
if (rst) begin
res_valid <= 0;
sr <= 0;
cnt <= 0;
start_cnt <= 0;
NEG_DIVISOR <= 0;
end else if (opn_valid && !res_valid) begin
abs_dividend = dividend[7] ? -dividend : dividend;
abs_divisor = divisor[7] ? -divisor : divisor;
sr = {abs_dividend, 1'b0};
NEG_DIVISOR = -abs_divisor;
...
functional details[stdout] Error: dividend=100, divisor= 10, expected=000a, got=0a00 Error: dividend=156, divisor= 10, expected=00f6, got=0a00 Error: dividend=100, divisor=246, expected=00f6, got=0a00 Error: dividend=156, divisor=246, expected=000a, got=0a00 Error: dividend=123, divisor=123, expected=0001, got=0a00 Error: dividend= 0, divisor=123, expected=0000, got=0a00 Error: dividend=123, divisor=251, expected=7b00, got=0a00 Error: dividend=255, divisor= 7, expected=0324, got=0a00 ===========Failed=========== 8 /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 335000 (1ps) synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260427_102437_171676_163c0c | ok | ok | ok | failed | failed | synthesis | OpenLane failed: 2 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v previewmodule radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] sr;
reg [7:0] cnt;
reg start_cnt;
reg NEG_DIVISOR;
reg [15:0] temp_result;
always @(posedge clk or posedge rst) begin
if (rst) begin
res_valid <= 0;
sr <= 0;
cnt <= 0;
start_cnt <= 0;
NEG_DIVISOR <= 0;
end else if (opn_valid && !res_valid) begin
abs_dividend = dividend[7] ? -dividend : dividend;
abs_divisor = divisor[7] ? -divisor : divisor;
sr = {abs_dividend, 1'b0};
NEG_DIVISOR = -abs_divisor;
...
functional details[stdout] Error: dividend=100, divisor= 10, expected=000a, got=0000 Error: dividend=156, divisor= 10, expected=00f6, got=0000 Error: dividend=100, divisor=246, expected=00f6, got=0000 Error: dividend=156, divisor=246, expected=000a, got=0000 Error: dividend=123, divisor=123, expected=0001, got=0000 Error: dividend=123, divisor=251, expected=7b00, got=0000 Error: dividend=255, divisor= 7, expected=0324, got=0000 ===========Failed=========== 7 /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 335000 (1ps) synthesis details[error] OpenLane failed: 2 errors[][
{
"stage": "openlane",
"code": "openlane.failed",
"message": "OpenLane failed: 2",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260427_102437_171676_163c0c | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v previewmodule verified_radix2_div (
input clk,
input rst,
input sign,
input [7:0] dividend,
input [7:0] divisor,
input opn_valid,
input res_ready,
output reg res_valid,
output reg [15:0] result
);
reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg neg_divisor;
reg [15:0] sr;
reg start_cnt;
reg [3:0] cnt;
wire [15:0] neg_sr;
wire [15:0] sub_result;
wire carry_out;
assign neg_sr = ~sr + 1;
assign sub_result = sr[15:0] - (neg_divisor ? neg_sr : sr);
assign carry_out = sub_result[15];
always @(posedge clk or posedge rst) begin
if (rst) begin
res_valid <= 0;
start_cnt <= 0;
cnt <= 0;
sr <= 0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div
3 error(s) during elaboration.
*** These modules were missing:
radix2_div referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:14: error: Unknown module type: radix2_div\n3 error(s) during elaboration.\n*** These modules were missing:\n radix2_div referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|