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deepseek-coder-v2:16b | RAG off

13_rtllm_miscellaneous / task_03 | freq_divbyfrac

benchmarkrtllm
task_idrtllm/13_rtllm_miscellaneous/task_03
samples_total10
final_success_samples10
final_success_rate_samples100.0%
functional_pass_rate_samples100.0%
synth_pass_rate_samples100.0%
source_runsrun_20260427_102437_171676_163c0c

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260427_102437_171676_163c0c ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_miscellaneous__task_03\samples\run_20260427_102437_171676_163c0c__sample_1
generated.v preview 
module freq_divbyfrac (
    input clk,
    input rst_n,
    output reg clk_div
);

parameter MUL2_DIV_CLK = 7;
reg [2:0] cnt;
reg [2:0] cnt_next;
reg clk1;
reg clk2;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cnt <= 3'b0;
        clk1 <= 1'b0;
        clk2 <= 1'b0;
    end else begin
        case (cnt)
            3'd0: begin
                cnt <= cnt + 1;
                clk1 <= 1'b1;
            end
            3'd1, 3'd2, 3'd3: begin
                cnt <= cnt + 1;
                clk1 <= 1'b1;
            end
            3'd4: begin
                cnt <= cnt + 1;
                clk1 <= 1'b0;
            end
            3'd5, 3'd6: begin
...
functional details 
[stdout]
Failed at          0: clk=1, clk_div=0 (expected           1)
Failed at          1: clk=0, clk_div=0 (expected           1)
Failed at          2: clk=1, clk_div=0 (expected           1)
Failed at          7: clk=0, clk_div=0 (expected           1)
Failed at         10: clk=1, clk_div=1 (expected           0)
Failed at         11: clk=0, clk_div=1 (expected           0)
Failed at         12: clk=1, clk_div=1 (expected           0)
Failed at         13: clk=0, clk_div=1 (expected           0)
Failed at         17: clk=0, clk_div=1 (expected           0)
=========== Test completed with           9/20 failures ===========
/workspace/banchmarks/rtllm/13_rtllm_miscellaneous/task_03/tb.v:27: $finish called at 130000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_2 run_20260427_102437_171676_163c0c ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_miscellaneous__task_03\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v preview 
module freq_divbyfrac (
    input clk,
    input rst_n,
    output reg clk_div
);

parameter MUL2_DIV_CLK = 7;
reg [2:0] cnt;
reg [2:0] next_cnt;
reg [3:0] phase1;
reg [3:0] phase2;
reg [3:0] next_phase1;
reg [3:0] next_phase2;
reg clk_div1;
reg clk_div2;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cnt <= 0;
        phase1 <= 0;
        phase2 <= 0;
        clk_div1 <= 0;
        clk_div2 <= 0;
    end else begin
        cnt <= next_cnt;
        phase1 <= next_phase1;
        phase2 <= next_phase2;
        if (cnt == MUL2_DIV_CLK - 1) begin
            cnt <= 0;
            clk_div1 <= ~clk_div1;
            clk_div2 <= ~clk_div2;
        end else begin
...
functional details 
[stdout]
Failed at          0: clk=1, clk_div=0 (expected           1)
Failed at          1: clk=0, clk_div=0 (expected           1)
Failed at          2: clk=1, clk_div=0 (expected           1)
Failed at          7: clk=0, clk_div=0 (expected           1)
Failed at          8: clk=1, clk_div=0 (expected           1)
Failed at          9: clk=0, clk_div=0 (expected           1)
Failed at         14: clk=1, clk_div=0 (expected           1)
Failed at         15: clk=0, clk_div=0 (expected           1)
Failed at         16: clk=1, clk_div=0 (expected           1)
=========== Test completed with           9/20 failures ===========
/workspace/banchmarks/rtllm/13_rtllm_miscellaneous/task_03/tb.v:27: $finish called at 130000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_3 run_20260427_102437_171676_163c0c ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_miscellaneous__task_03\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v preview 
module freq_divbyfrac (
    input clk,
    input rst_n,
    output reg clk_div
);

parameter MUL2_DIV_CLK = 7;
reg [2:0] count;
reg [2:0] next_count;
reg [2:0] phase1;
reg [2:0] phase2;
reg div_clk1;
reg div_clk2;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count <= 3'b0;
        next_count <= 3'b0;
        phase1 <= 3'b0;
        phase2 <= 3'b0;
        div_clk1 <= 1'b0;
        div_clk2 <= 1'b0;
    end else begin
        count <= next_count;
        if (count == 3'd6) begin
            phase1 <= count + 3'd1;
            phase2 <= count - 3'd1;
            div_clk1 <= ~div_clk1;
            div_clk2 <= ~div_clk2;
        end else if (count == 3'd0) begin
            phase1 <= count + 3'd1;
            phase2 <= count - 3'd1;
...
functional details 
[stdout]
Failed at          0: clk=1, clk_div=0 (expected           1)
Failed at          1: clk=0, clk_div=0 (expected           1)
Failed at          2: clk=1, clk_div=0 (expected           1)
Failed at          7: clk=0, clk_div=0 (expected           1)
Failed at          8: clk=1, clk_div=0 (expected           1)
Failed at          9: clk=0, clk_div=0 (expected           1)
Failed at         14: clk=1, clk_div=0 (expected           1)
Failed at         15: clk=0, clk_div=0 (expected           1)
Failed at         16: clk=1, clk_div=0 (expected           1)
=========== Test completed with           9/20 failures ===========
/workspace/banchmarks/rtllm/13_rtllm_miscellaneous/task_03/tb.v:27: $finish called at 130000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_4 run_20260427_102437_171676_163c0c ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_miscellaneous__task_03\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v preview 
module freq_divbyfrac (
    input clk,
    input rst_n,
    output reg clk_div
);

parameter MUL2_DIV_CLK = 7; // Multiplier for division by fractional value
reg [2:0] count; // Counter to divide the clock
reg [2:0] count_next; // Next state of the counter
reg clk1, clk2; // Intermediate divided clocks

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count <= 3'b0;
        clk1 <= 1'b0;
        clk2 <= 1'b0;
    end else begin
        case (count)
            3'd0: begin // First half cycle with 4 source clock cycles
                count_next = 3'd1;
                clk1 = 1'b1;
            end
            3'd1: begin // Full cycle with 7 source clock cycles
                count_next = 3'd2;
                clk1 = 1'b1;
            end
            3'd2: begin // Second half cycle with 3 source clock cycles
                count_next = 3'd3;
                clk1 = 1'b0;
            end
            3'd3: begin // Full cycle with 7 source clock cycles
                count_next = 3'd4;
...
functional details 
[stdout]
Failed at          4: clk=1, clk_div=1 (expected           0)
Failed at          5: clk=0, clk_div=1 (expected           0)
Failed at          6: clk=1, clk_div=1 (expected           0)
Failed at          7: clk=0, clk_div=0 (expected           1)
Failed at         10: clk=1, clk_div=1 (expected           0)
Failed at         12: clk=1, clk_div=1 (expected           0)
Failed at         13: clk=0, clk_div=1 (expected           0)
Failed at         15: clk=0, clk_div=0 (expected           1)
Failed at         17: clk=0, clk_div=1 (expected           0)
Failed at         18: clk=1, clk_div=1 (expected           0)
=========== Test completed with          10/20 failures ===========
/workspace/banchmarks/rtllm/13_rtllm_miscellaneous/task_03/tb.v:27: $finish called at 130000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_5 run_20260427_102437_171676_163c0c ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_miscellaneous__task_03\samples\run_20260427_102437_171676_163c0c__sample_5
generated.v preview 
module freq_divbyfrac (
    input clk,
    input rst_n,
    output reg clk_div
);

parameter MUL2_DIV_CLK = 7;
reg [2:0] count;
reg [2:0] next_count;
reg [2:0] phase1;
reg [2:0] phase2;
reg [2:0] next_phase1;
reg [2:0] next_phase2;
reg clk_div1;
reg clk_div2;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count <= 3'b0;
        phase1 <= 3'b0;
        phase2 <= 3'b0;
    end else begin
        count <= next_count;
        phase1 <= next_phase1;
        phase2 <= next_phase2;
    end
end

always @(*) begin
    if (count == MUL2_DIV_CLK - 1) begin
        next_count = 3'b0;
    end else begin
...
functional details 
[stdout]
Failed at          3: clk=0, clk_div=1 (expected           0)
Failed at          4: clk=1, clk_div=1 (expected           0)
Failed at          5: clk=0, clk_div=1 (expected           0)
Failed at          7: clk=0, clk_div=0 (expected           1)
Failed at          8: clk=1, clk_div=0 (expected           1)
Failed at          9: clk=0, clk_div=0 (expected           1)
Failed at         12: clk=1, clk_div=1 (expected           0)
Failed at         13: clk=0, clk_div=1 (expected           0)
Failed at         17: clk=0, clk_div=1 (expected           0)
Failed at         18: clk=1, clk_div=1 (expected           0)
Failed at         19: clk=0, clk_div=1 (expected           0)
=========== Test completed with          11/20 failures ===========
/workspace/banchmarks/rtllm/13_rtllm_miscellaneous/task_03/tb.v:27: $finish called at 130000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_6 run_20260427_102437_171676_163c0c ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_miscellaneous__task_03\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v preview 
module freq_divbyfrac (
    input clk,
    input rst_n,
    output reg clk_div
);

parameter MUL2_DIV_CLK = 7; // Multiplier for division by fractional value
reg [2:0] count; // Counter to divide the clock
reg [2:0] next_count; // Next state of the counter
reg div1, div2; // Intermediate divided clocks
reg div1_delayed, div2_delayed; // Delayed versions of intermediate divided clocks

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count <= 0;
        div1 <= 0;
        div2 <= 0;
        div1_delayed <= 0;
        div2_delayed <= 0;
    end else begin
        case (count)
            3'b000: begin // First cycle, generate two uneven clock periods
                count <= count + 1;
                div1 <= 1;
                div2 <= 1;
            end
            3'b001: begin // Second cycle, adjust the first period to be shorter
                count <= count + 1;
                div1 <= 0;
                div2 <= 1;
            end
            3'b010: begin // Third cycle, generate phase-shifted versions of the divided clocks
...
functional details 
[stdout]
Failed at          2: clk=1, clk_div=0 (expected           1)
Failed at          4: clk=1, clk_div=1 (expected           0)
Failed at          5: clk=0, clk_div=1 (expected           0)
Failed at          7: clk=0, clk_div=0 (expected           1)
Failed at         12: clk=1, clk_div=1 (expected           0)
Failed at         13: clk=0, clk_div=1 (expected           0)
Failed at         16: clk=1, clk_div=0 (expected           1)
Failed at         18: clk=1, clk_div=1 (expected           0)
Failed at         19: clk=0, clk_div=1 (expected           0)
=========== Test completed with           9/20 failures ===========
/workspace/banchmarks/rtllm/13_rtllm_miscellaneous/task_03/tb.v:27: $finish called at 130000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_7 run_20260427_102437_171676_163c0c ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_miscellaneous__task_03\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v preview 
module freq_divbyfrac (
    input clk,
    input rst_n,
    output reg clk_div
);

parameter MUL2_DIV_CLK = 7;
reg [2:0] cnt;
reg [2:0] next_cnt;
reg clk1;
reg clk2;
reg clk3;
reg clk4;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        cnt <= 0;
    end else begin
        cnt <= next_cnt;
    end
end

always @(*) begin
    case (cnt)
        3'd0, 3'd1, 3'd2: next_cnt = cnt + 1'b1;
        3'd3: next_cnt = 3'd4;
        3'd4, 3'd5, 3'd6: next_cnt = cnt + 1'b1;
        default: next_cnt = 3'd0;
    endcase
end

always @(posedge clk or negedge rst_n) begin
...
functional details 
[stdout]
Failed at          0: clk=1, clk_div=0 (expected           1)
Failed at          1: clk=0, clk_div=0 (expected           1)
Failed at          2: clk=1, clk_div=0 (expected           1)
Failed at          7: clk=0, clk_div=0 (expected           1)
Failed at          8: clk=1, clk_div=0 (expected           1)
Failed at          9: clk=0, clk_div=0 (expected           1)
Failed at         12: clk=1, clk_div=1 (expected           0)
Failed at         13: clk=0, clk_div=1 (expected           0)
Failed at         17: clk=0, clk_div=1 (expected           0)
Failed at         18: clk=1, clk_div=1 (expected           0)
Failed at         19: clk=0, clk_div=1 (expected           0)
=========== Test completed with          11/20 failures ===========
/workspace/banchmarks/rtllm/13_rtllm_miscellaneous/task_03/tb.v:27: $finish called at 130000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_8 run_20260427_102437_171676_163c0c ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_miscellaneous__task_03\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v preview 
module freq_divbyfrac (
    input clk,
    input rst_n,
    output reg clk_div
);

parameter MUL2_DIV_CLK = 7;
reg [2:0] count;
reg [2:0] next_count;
reg [2:0] phase1;
reg [2:0] phase2;
reg [2:0] next_phase1;
reg [2:0] next_phase2;
reg clk_div1;
reg clk_div2;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count <= 3'b0;
        phase1 <= 3'b0;
        phase2 <= 3'b0;
    end else begin
        count <= next_count;
        phase1 <= next_phase1;
        phase2 <= next_phase2;
    end
end

always @(*) begin
    if (count == MUL2_DIV_CLK - 1) begin
        next_count = 3'b0;
    end else begin
...
functional details 
[stdout]
Failed at          0: clk=1, clk_div=0 (expected           1)
Failed at          1: clk=0, clk_div=0 (expected           1)
Failed at          2: clk=1, clk_div=0 (expected           1)
Failed at          7: clk=0, clk_div=0 (expected           1)
Failed at          8: clk=1, clk_div=0 (expected           1)
Failed at          9: clk=0, clk_div=0 (expected           1)
Failed at         14: clk=1, clk_div=0 (expected           1)
Failed at         15: clk=0, clk_div=0 (expected           1)
Failed at         16: clk=1, clk_div=0 (expected           1)
=========== Test completed with           9/20 failures ===========
/workspace/banchmarks/rtllm/13_rtllm_miscellaneous/task_03/tb.v:27: $finish called at 130000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_9 run_20260427_102437_171676_163c0c ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_miscellaneous__task_03\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v preview 
module freq_divbyfrac (
    input clk,
    input rst_n,
    output reg clk_div
);

parameter MUL2_DIV_CLK = 7;
reg [2:0] count;
reg [2:0] next_count;
reg [2:0] phase1;
reg [2:0] phase2;
reg div_clk1;
reg div_clk2;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count <= 3'b0;
        next_count <= 3'b0;
        phase1 <= 3'b0;
        phase2 <= 3'b0;
        div_clk1 <= 1'b0;
        div_clk2 <= 1'b0;
    end else begin
        count <= next_count;
        if (count == 3'd6) begin
            phase1 <= count + 3'd1;
            phase2 <= count - 3'd1;
            div_clk1 <= ~div_clk1;
            div_clk2 <= ~div_clk2;
        end else if (count == 3'd0) begin
            phase1 <= count + 3'd1;
            phase2 <= count - 3'd1;
...
functional details 
[stdout]
Failed at          0: clk=1, clk_div=0 (expected           1)
Failed at          1: clk=0, clk_div=0 (expected           1)
Failed at          2: clk=1, clk_div=0 (expected           1)
Failed at          7: clk=0, clk_div=0 (expected           1)
Failed at          8: clk=1, clk_div=0 (expected           1)
Failed at          9: clk=0, clk_div=0 (expected           1)
Failed at         14: clk=1, clk_div=0 (expected           1)
Failed at         15: clk=0, clk_div=0 (expected           1)
Failed at         16: clk=1, clk_div=0 (expected           1)
=========== Test completed with           9/20 failures ===========
/workspace/banchmarks/rtllm/13_rtllm_miscellaneous/task_03/tb.v:27: $finish called at 130000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_10 run_20260427_102437_171676_163c0c ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_miscellaneous__task_03\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v preview 
module freq_divbyfrac (
    input clk,
    input rst_n,
    output reg clk_div
);

parameter MUL2_DIV_CLK = 7;
reg [2:0] count;
reg [2:0] next_count;
reg [2:0] phase1;
reg [2:0] phase2;
reg [2:0] next_phase1;
reg [2:0] next_phase2;
reg clk_div1;
reg clk_div2;

always @(posedge clk or negedge rst_n) begin
    if (!rst_n) begin
        count <= 3'b0;
        phase1 <= 3'b0;
        phase2 <= 3'b0;
    end else begin
        count <= next_count;
        phase1 <= next_phase1;
        phase2 <= next_phase2;
    end
end

always @(*) begin
    if (count == MUL2_DIV_CLK - 1) begin
        next_count = 3'b0;
    end else begin
...
functional details 
[stdout]
Failed at          3: clk=0, clk_div=1 (expected           0)
Failed at          4: clk=1, clk_div=1 (expected           0)
Failed at          5: clk=0, clk_div=1 (expected           0)
Failed at          6: clk=1, clk_div=1 (expected           0)
Failed at          8: clk=1, clk_div=0 (expected           1)
Failed at          9: clk=0, clk_div=0 (expected           1)
Failed at         12: clk=1, clk_div=1 (expected           0)
Failed at         13: clk=0, clk_div=1 (expected           0)
Failed at         17: clk=0, clk_div=1 (expected           0)
Failed at         18: clk=1, clk_div=1 (expected           0)
Failed at         19: clk=0, clk_div=1 (expected           0)
=========== Test completed with          11/20 failures ===========
/workspace/banchmarks/rtllm/13_rtllm_miscellaneous/task_03/tb.v:27: $finish called at 130000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}