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deepseek-coder-v2:16b | RAG on

06_reset_domain_crossing / task_61 | ordered_reset_ctrl

benchmarkilyasov
task_idilyasov/06_reset_domain_crossing/task_61
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260426_224416_826723_5f6af1

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260426_224416_826723_5f6af1__sample_1
generated.v preview 
module ordered_reset_ctrl (
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

reg [1:0] sync_rst_a;
reg [1:0] sync_rst_b;
wire ready_a;

// Reset synchronizer for clk_a
always @(posedge clk_a or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_a <= 2'b00;
    end else begin
        sync_rst_a[0] <= 1'b0;
        sync_rst_a[1] <= sync_rst_a[0];
    end
end

assign ready_a = (sync_rst_a == 2'b11);

// Reset synchronizer for clk_b
always @(posedge clk_b or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_b <= 2'b00;
        rst_b_n <= 1'b1;
    end else begin
        sync_rst_b[0] <= ready_a ? 1'b0 : 1'b1;
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B released before a_init_done was asserted.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260426_224416_826723_5f6af1__sample_2
generated.v preview 
module ordered_reset_ctrl (
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

reg [1:0] sync_rst_a;
reg [1:0] sync_rst_b;
wire ready_a;

assign ready_a = ~sync_rst_a[1];

always @(posedge clk_a or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_a <= 2'b00;
        rst_a_n <= 1'b0;
    end else begin
        sync_rst_a[0] <= 1'b1;
        sync_rst_a[1] <= sync_rst_a[0];
        if (!ready_a) begin
            rst_a_n <= 1'b0;
        end else begin
            rst_a_n <= ~sync_rst_a[1];
        end
    end
end

always @(posedge clk_b or negedge arst_n) begin
    if (!arst_n) begin
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B released after only one clk_b synchronizer stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: domain A released reset after only one clk_a edge.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260426_224416_826723_5f6af1__sample_3
generated.v preview 
module ordered_reset_ctrl (
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

reg [1:0] sync_rst_a;
reg [1:0] sync_rst_b;
wire ready_a;

// Reset synchronizer for clk_a
always @(posedge clk_a or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_a <= 2'b11;
    end else if (sync_rst_a == 2'b00) begin
        sync_rst_a <= 2'b00;
    end else begin
        sync_rst_a <= {sync_rst_a[0], 1'b0};
    end
end

assign ready_a = (sync_rst_a == 2'b00) & a_init_done;

// Reset synchronizer for clk_b
always @(posedge clk_b or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_b <= 2'b11;
    end else if (sync_rst_b == 2'b00 && ready_a) begin
        sync_rst_b <= 2'b00;
...
functional details 
[stdout]
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B did not release after the second clk_b stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: domain A released reset after only one clk_a edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260426_224416_826723_5f6af1__sample_4
generated.v preview 
module ordered_reset_ctrl (
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

reg [1:0] sync_rst_a;
reg [1:0] sync_rst_b;
wire ready_a;

// Reset synchronizer for clk_a
always @(posedge clk_a or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_a <= 2'b11;
    end else if (a_init_done) begin
        sync_rst_a <= {sync_rst_a[0], 1'b1};
    end else begin
        sync_rst_a <= {sync_rst_a[0], sync_rst_a[1]};
    end
end

assign ready_a = (sync_rst_a == 2'b01);

// Reset synchronizer for clk_b
always @(posedge clk_b or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_b <= 2'b11;
    end else if (ready_a) begin
        sync_rst_b <= {sync_rst_b[0], 1'b1};
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B released after only one clk_b synchronizer stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260426_224416_826723_5f6af1__sample_5
generated.v preview 
module ordered_reset_ctrl(
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

reg [1:0] sync_rst_a;
reg [1:0] sync_rst_b;
wire ready_a;

assign ready_a = ~sync_rst_a[1];

always @(posedge clk_a or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_a <= 2'b00;
        rst_a_n <= 1'b1;
    end else begin
        sync_rst_a[0] <= 1'b0;
        sync_rst_a[1] <= sync_rst_a[0];
        if (sync_rst_a[1]) rst_a_n <= 1'b0;
        else rst_a_n <= 1'b1;
    end
end

always @(posedge clk_b or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_b <= 2'b11;
        rst_b_n <= 1'b1;
    end else begin
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain B released after only one clk_b synchronizer stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: domain A released reset after only one clk_a edge.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260426_224416_826723_5f6af1__sample_6
generated.v preview 
module ordered_reset_ctrl (
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

reg [1:0] sync_rst_a;
reg [1:0] sync_rst_b;
wire ready_a;

// Reset synchronizer for clk_a
always @(posedge clk_a or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_a <= 2'b11;
    end else if (sync_rst_a == 2'b00) begin
        sync_rst_a <= 2'b00;
    end else begin
        sync_rst_a <= {sync_rst_a[0], 1'b0};
    end
end

assign ready_a = (sync_rst_a == 2'b00);

// Reset synchronizer for clk_b
always @(posedge clk_b or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_b <= 2'b11;
    end else if (sync_rst_b == 2'b00 && ready_a) begin
        sync_rst_b <= {sync_rst_b[0], 1'b0};
...
functional details 
[stdout]
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B released after only one clk_b synchronizer stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: domain A released reset after only one clk_a edge.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260426_224416_826723_5f6af1__sample_7
generated.v preview 
module ordered_reset_ctrl (
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

reg [1:0] sync_rst_a;
reg [1:0] sync_rst_b;
wire ready_a;

// Reset synchronizer for clk_a
always @(posedge clk_a or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_a <= 2'b11;
    end else if (a_init_done) begin
        sync_rst_a <= {sync_rst_a[0], 1'b1};
    end else begin
        sync_rst_a <= {sync_rst_a[0], sync_rst_a[1]};
    end
end

assign ready_a = sync_rst_a[1];

// Reset synchronizer for clk_b
always @(posedge clk_b or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_b <= 2'b11;
    end else if (ready_a) begin
        sync_rst_b <= {sync_rst_b[0], 1'b1};
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B did not release after the second clk_b stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: domain A did not release reset after two clk_a edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260426_224416_826723_5f6af1__sample_8
generated.v preview 
module ordered_reset_ctrl (
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

reg [1:0] sync_rst_a;
reg [1:0] sync_rst_b;
wire ready_a;

// Reset synchronizer for clk_a
always @(posedge clk_a or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_a <= 2'b11;
    end else if (sync_rst_a == 2'b00) begin
        sync_rst_a <= 2'b00;
    end else begin
        sync_rst_a <= {sync_rst_a[0], 1'b0};
    end
end

assign ready_a = (sync_rst_a == 2'b00);

// Reset synchronizer for clk_b
always @(posedge clk_b or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_b <= 2'b11;
    end else if (sync_rst_b == 2'b00 && ready_a) begin
        sync_rst_b <= {sync_rst_b[0], 1'b0};
...
functional details 
[stdout]
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B did not release after the second clk_b stage.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: domain A did not release reset after two clk_a edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260426_224416_826723_5f6af1__sample_9
generated.v preview 
module ordered_reset_ctrl (
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

reg [1:0] sync_rst_a;
reg [1:0] sync_rst_b;
wire ready_a;

// Reset synchronizer for clk_a
always @(posedge clk_a or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_a <= 2'b11;
    end else if (a_init_done) begin
        sync_rst_a <= {sync_rst_a[0], 1'b1};
    end else begin
        sync_rst_a <= {sync_rst_a[0], sync_rst_a[1]};
    end
end

assign ready_a = sync_rst_a[1];

// Reset synchronizer for clk_b
always @(posedge clk_b or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_b <= 2'b11;
    end else if (ready_a) begin
        sync_rst_b <= {sync_rst_b[0], 1'b1};
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A did not release reset after two clk_a edges.
ERROR: domain B did not release after the second clk_b stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_61\samples\run_20260426_224416_826723_5f6af1__sample_10
generated.v preview 
module ordered_reset_ctrl (
    input clk_a,
    input clk_b,
    input arst_n,
    input a_init_done,
    output reg rst_a_n,
    output reg rst_b_n
);

reg [1:0] sync_rst_a;
reg [1:0] sync_rst_b;
wire ready_a;

// Reset synchronizer for clk_a
always @(posedge clk_a or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_a <= 2'b11;
    end else if (sync_rst_a == 2'b00) begin
        sync_rst_a <= 2'b00;
    end else begin
        sync_rst_a <= {sync_rst_a[0], 1'b0};
    end
end

assign ready_a = (sync_rst_a == 2'b00);

// Reset synchronizer for clk_b
always @(posedge clk_b or negedge arst_n) begin
    if (!arst_n) begin
        sync_rst_b <= 2'b11;
    end else if (sync_rst_b == 2'b00 && ready_a) begin
        sync_rst_b <= {sync_rst_b[0], 1'b0};
...
functional details 
[stdout]
ERROR: resets were not asserted at power-up.
ERROR: domain A released reset after only one clk_a edge.
ERROR: domain B released before a_init_done was asserted.
ERROR: domain B deasserted reset asynchronously from an A-domain signal.
ERROR: domain B released after only one clk_b synchronizer stage.
ERROR: asynchronous reset assertion did not immediately reset both domains.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_61/tb.v:106: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: resets were not asserted at power-up.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}