Назад к моделям Назад к профилю модели

deepseek-coder-v2:16b | RAG on

06_reset_domain_crossing / task_62 | triple_reset_sequencer

benchmarkilyasov
task_idilyasov/06_reset_domain_crossing/task_62
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260426_224416_826723_5f6af1

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_224416_826723_5f6af1__sample_1
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

reg rst_cpu_meta1, rst_cpu_meta2;
always @(posedge clk_cpu or negedge arst_n) begin
    if (!arst_n) begin
        rst_cpu_meta1 <= 0;
        rst_cpu_meta2 <= 0;
    end else begin
        rst_cpu_meta1 <= 1'b0;
        rst_cpu_meta2 <= rst_cpu_meta1;
    end
end
assign rst_cpu_n = ~rst_cpu_meta2;

reg rst_bus_meta1, rst_bus_meta2;
always @(posedge clk_bus or negedge arst_n) begin
    if (!arst_n) begin
        rst_bus_meta1 <= 0;
        rst_bus_meta2 <= 0;
    end else begin
        rst_bus_meta1 <= 1'b0;
        rst_bus_meta2 <= rst_bus_meta1;
    end
end
...
functional details 
[stdout]
ERROR: not all domains were held in reset during global reset.
ERROR: CPU reset released after one edge instead of two.
ERROR: downstream domains released before CPU was safely active.
ERROR: BUS reset released after one synchronizer stage.
ERROR: PERIPH reset released before BUS reset was synchronized.
ERROR: PERIPH reset released after one synchronizer stage.
ERROR: asynchronous reassertion did not drop all local resets immediately.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: not all domains were held in reset during global reset.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_224416_826723_5f6af1__sample_2
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

reg rst_cpu_meta0, rst_cpu_meta1;
reg rst_bus_meta0, rst_bus_meta1;
reg rst_periph_meta0, rst_periph_meta1;

always @(posedge clk_cpu or negedge arst_n) begin
    if (!arst_n) begin
        rst_cpu_meta0 <= 1'b0;
        rst_cpu_meta1 <= 1'b0;
    end else begin
        rst_cpu_meta0 <= 1'b0;
        rst_cpu_meta1 <= rst_cpu_meta0;
    end
end

assign rst_cpu_n = rst_cpu_meta1;

always @(posedge clk_bus or negedge arst_n) begin
    if (!arst_n) begin
        rst_bus_meta0 <= 1'b0;
        rst_bus_meta1 <= 1'b0;
    end else begin
        rst_bus_meta0 <= 1'b0;
...
functional details 
[stdout]
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_224416_826723_5f6af1__sample_3
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

reg rst_cpu_meta1, rst_cpu_meta2;
reg rst_bus_meta1, rst_bus_meta2;
reg rst_periph_meta1, rst_periph_meta2;

always @(posedge clk_cpu or negedge arst_n) begin
    if (!arst_n) begin
        rst_cpu_meta1 <= 0;
        rst_cpu_meta2 <= 0;
    end else begin
        rst_cpu_meta1 <= 0;
        rst_cpu_meta2 <= rst_cpu_meta1;
    end
end

assign rst_cpu_n = rst_cpu_meta2;

always @(posedge clk_bus or negedge arst_n) begin
    if (!arst_n) begin
        rst_bus_meta1 <= 0;
        rst_bus_meta2 <= 0;
    end else begin
        rst_bus_meta1 <= 0;
...
functional details 
[stdout]
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_224416_826723_5f6af1__sample_4
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

reg rst_cpu_meta0, rst_cpu_meta1;
reg rst_bus_meta0, rst_bus_meta1;
reg rst_periph_meta0, rst_periph_meta1;

always @(posedge clk_cpu or negedge arst_n) begin
    if (!arst_n) begin
        rst_cpu_meta0 <= 1'b0;
        rst_cpu_meta1 <= 1'b0;
    end else begin
        rst_cpu_meta0 <= 1'b0;
        rst_cpu_meta1 <= rst_cpu_meta0;
    end
end

assign rst_cpu_n = rst_cpu_meta1;

always @(posedge clk_bus or negedge arst_n) begin
    if (!arst_n) begin
        rst_bus_meta0 <= 1'b0;
        rst_bus_meta1 <= 1'b0;
    end else begin
        rst_bus_meta0 <= 1'b0;
...
functional details 
[stdout]
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_224416_826723_5f6af1__sample_5
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

reg rst_cpu_meta0, rst_cpu_meta1;
reg rst_bus_meta0, rst_bus_meta1;
reg rst_periph_meta0, rst_periph_meta1;

always @(posedge clk_cpu or negedge arst_n) begin
    if (!arst_n) begin
        rst_cpu_meta0 <= 1'b0;
        rst_cpu_meta1 <= 1'b0;
    end else begin
        rst_cpu_meta0 <= 1'b0;
        rst_cpu_meta1 <= rst_cpu_meta0;
    end
end

assign rst_cpu_n = rst_cpu_meta1;

always @(posedge clk_bus or negedge arst_n) begin
    if (!arst_n) begin
        rst_bus_meta0 <= 1'b0;
        rst_bus_meta1 <= 1'b0;
    end else begin
        rst_bus_meta0 <= 1'b0;
...
functional details 
[stdout]
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_224416_826723_5f6af1__sample_6
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

reg rst_cpu_meta1, rst_cpu_meta2;
reg rst_bus_meta1, rst_bus_meta2;
reg rst_periph_meta1, rst_periph_meta2;

always @(posedge clk_cpu or negedge arst_n) begin
    if (!arst_n) begin
        rst_cpu_meta1 <= 0;
        rst_cpu_meta2 <= 0;
    end else begin
        rst_cpu_meta1 <= 0;
        rst_cpu_meta2 <= rst_cpu_meta1;
    end
end

assign rst_cpu_n = rst_cpu_meta2;

always @(posedge clk_bus or negedge arst_n) begin
    if (!arst_n) begin
        rst_bus_meta1 <= 0;
        rst_bus_meta2 <= 0;
    end else begin
        rst_bus_meta1 <= 0;
...
functional details 
[stdout]
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_224416_826723_5f6af1__sample_7
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

reg rst_cpu_meta0, rst_cpu_meta1;
reg rst_bus_meta0, rst_bus_meta1;
reg rst_periph_meta0, rst_periph_meta1;

always @(posedge clk_cpu or negedge arst_n) begin
    if (!arst_n) begin
        rst_cpu_meta0 <= 1'b0;
        rst_cpu_meta1 <= 1'b0;
    end else begin
        rst_cpu_meta0 <= 1'b0;
        rst_cpu_meta1 <= rst_cpu_meta0;
    end
end

assign rst_cpu_n = rst_cpu_meta1;

always @(posedge clk_bus or negedge arst_n) begin
    if (!arst_n) begin
        rst_bus_meta0 <= 1'b0;
        rst_bus_meta1 <= 1'b0;
    end else begin
        rst_bus_meta0 <= 1'b0;
...
functional details 
[stdout]
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_224416_826723_5f6af1__sample_8
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

reg rst_cpu_meta1, rst_cpu_meta2;
reg rst_bus_meta1, rst_bus_meta2;
reg rst_periph_meta1, rst_periph_meta2;

always @(posedge clk_cpu or negedge arst_n) begin
    if (!arst_n) begin
        rst_cpu_meta1 <= 0;
        rst_cpu_meta2 <= 0;
    end else begin
        rst_cpu_meta1 <= 0;
        rst_cpu_meta2 <= rst_cpu_meta1;
    end
end

assign rst_cpu_n = rst_cpu_meta2;

always @(posedge clk_bus or negedge arst_n) begin
    if (!arst_n) begin
        rst_bus_meta1 <= 0;
        rst_bus_meta2 <= 0;
    end else begin
        rst_bus_meta1 <= 0;
...
functional details 
[stdout]
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_224416_826723_5f6af1__sample_9
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

reg rst_cpu_meta0, rst_cpu_meta1;
reg rst_bus_meta0, rst_bus_meta1;
reg rst_periph_meta0, rst_periph_meta1;

always @(posedge clk_cpu or negedge arst_n) begin
    if (!arst_n) begin
        rst_cpu_meta0 <= 1'b0;
        rst_cpu_meta1 <= 1'b0;
    end else begin
        rst_cpu_meta0 <= 1'b0;
        rst_cpu_meta1 <= rst_cpu_meta0;
    end
end

assign rst_cpu_n = rst_cpu_meta1;

always @(posedge clk_bus or negedge arst_n) begin
    if (!arst_n) begin
        rst_bus_meta0 <= 1'b0;
        rst_bus_meta1 <= 1'b0;
    end else begin
        rst_bus_meta0 <= 1'b0;
...
functional details 
[stdout]
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_62\samples\run_20260426_224416_826723_5f6af1__sample_10
generated.v preview 
module triple_reset_sequencer (
    input clk_cpu,
    input clk_bus,
    input clk_periph,
    input arst_n,
    output rst_cpu_n,
    output rst_bus_n,
    output rst_periph_n
);

reg rst_cpu_meta1, rst_cpu_meta2;
reg rst_bus_meta1, rst_bus_meta2;
reg rst_periph_meta1, rst_periph_meta2;

always @(posedge clk_cpu or negedge arst_n) begin
    if (!arst_n) begin
        rst_cpu_meta1 <= 0;
        rst_cpu_meta2 <= 0;
    end else begin
        rst_cpu_meta1 <= 0;
        rst_cpu_meta2 <= rst_cpu_meta1;
    end
end

assign rst_cpu_n = rst_cpu_meta2;

always @(posedge clk_bus or negedge arst_n) begin
    if (!arst_n) begin
        rst_bus_meta1 <= 0;
        rst_bus_meta2 <= 0;
    end else begin
        rst_bus_meta1 <= 0;
...
functional details 
[stdout]
ERROR: CPU reset did not release after two clk_cpu edges.
ERROR: BUS reset did not release after the second synchronized stage.
ERROR: PERIPH reset did not release after two synchronized stages.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_62/tb.v:119: $finish called at 78000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: CPU reset did not release after two clk_cpu edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}