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deepseek-coder-v2:16b | RAG on

07_csr_register_map_generation / task_72 | axil_sensor_csr

benchmarkilyasov
task_idilyasov/07_csr_register_map_generation/task_72
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260426_224416_826723_5f6af1

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_224416_826723_5f6af1__sample_1
generated.v preview 
module axil_sensor_csr (
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output reg awready = 0,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output reg wready = 0,
    output reg [1:0] bresp = 2'b00,
    output reg bvalid = 0,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output reg arready = 0,
    output reg [31:0] rdata = 32'd0,
    output reg [1:0] rresp = 2'b00,
    output reg rvalid = 0,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output reg block_enable = 0,
    output reg [7:0] gain = 8'd0,
    output reg kick_pulse = 0,
    output reg irq_sticky = 0
);

    typedef enum {IDLE, WRITE, READ} state_t;
    state_t state, next_state;

    always @(posedge clk or negedge rst_n) begin
...
functional details 
[stdout]
ERROR: reset values are incorrect.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL bit 0 failed.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000
ERROR: irq_evt did not set irq_sticky.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000000
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: writing 0 incorrectly cleared irq_sticky.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready for CMD write.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: kick_pulse did not assert on CMD write.
ERROR: AXI-Lite read channel was not ready in idle state.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_224416_826723_5f6af1__sample_2
generated.v preview 
module axil_sensor_csr (
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output reg awready = 0,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output reg wready = 0,
    output reg [1:0] bresp = 2'b00,
    output reg bvalid = 0,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output reg arready = 0,
    output reg [31:0] rdata = 32'd0,
    output reg [1:0] rresp = 2'b00,
    output reg rvalid = 0,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output reg block_enable = 0,
    output reg [7:0] gain = 8'd0,
    output reg kick_pulse = 0,
    output reg irq_sticky = 0
);

reg [31:0] ctrl;
reg [31:0] status;
reg cmd;
...
functional details 
[stdout]
ERROR: reset values are incorrect.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL bit 0 failed.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: STATUS read without IRQ bit set returned wrong value. Got 0000005c
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: STATUS read with IRQ bit set returned wrong value. Got 0000015c
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: writing 0 incorrectly cleared irq_sticky.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready for CMD write.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: AXI-Lite read channel was not ready in idle state.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write channel was not ready in idle state.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_224416_826723_5f6af1__sample_3
generated.v preview 
module axil_sensor_csr (
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output reg awready = 0,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output reg wready = 0,
    output reg [1:0] bresp = 2'b00,
    output reg bvalid = 0,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output reg arready = 0,
    output reg [31:0] rdata = 32'd0,
    output reg [1:0] rresp = 2'b00,
    output reg rvalid = 0,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output reg block_enable = 0,
    output reg [7:0] gain = 8'd8,
    output reg kick_pulse = 0,
    output reg irq_sticky = 0
);

    // Register addresses and fields
    typedef enum logic [2:0] {
        CTRL_REG   = 3'h0,
        STATUS_REG = 3'h1,
...
functional details 
[stdout]
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL bit 0 failed.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: STATUS read without IRQ bit set returned wrong value. Got 0000002a
ERROR: irq_evt did not set irq_sticky.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: STATUS read with IRQ bit set returned wrong value. Got 0000002a
ERROR: AXI-Lite write response was not generated correctly.
ERROR: writing 0 incorrectly cleared irq_sticky.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: kick_pulse did not assert on CMD write.
ERROR: AXI-Lite read response was not generated correctly.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write channel was not ready in idle state.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write channel was not ready in idle state.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_224416_826723_5f6af1__sample_4
generated.v preview 
module axil_sensor_csr (
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output reg awready = 0,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output reg wready = 0,
    output reg [1:0] bresp = 2'b00,
    output reg bvalid = 0,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output reg arready = 0,
    output reg [31:0] rdata = 0,
    output reg [1:0] rresp = 2'b00,
    output reg rvalid = 0,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output reg block_enable = 0,
    output reg [7:0] gain = 8,
    output reg kick_pulse = 0,
    output reg irq_sticky = 0
);

    // Register addresses
    localparam CTRL_ADDR = 8'h00;
    localparam STATUS_ADDR = 8'h04;
    localparam CMD_ADDR = 8'h08;
...
functional details 
[stdout]
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL bit 0 failed.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000
ERROR: irq_evt did not set irq_sticky.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000001
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: writing 0 incorrectly cleared irq_sticky.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready for CMD write.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: kick_pulse did not assert on CMD write.
ERROR: AXI-Lite read channel was not ready in idle state.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write channel was not ready in idle state.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write channel was not ready in idle state.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_224416_826723_5f6af1__sample_5
generated.v preview 
module axil_sensor_csr (
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output reg awready = 0,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output reg wready = 0,
    output reg [1:0] bresp = 2'b00,
    output reg bvalid = 0,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output reg arready = 0,
    output reg [31:0] rdata = 0,
    output reg [1:0] rresp = 2'b00,
    output reg rvalid = 0,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output reg block_enable = 0,
    output reg [7:0] gain = 8,
    output reg kick_pulse = 0,
    output reg irq_sticky = 0
);

    // Register addresses and fields
    localparam CTRL_ADDR = 8'h00;
    localparam STATUS_ADDR = 8'h04;
    localparam CMD_ADDR = 8'h08;
...
functional details 
[stdout]
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL bit 0 failed.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000000
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: W1C clear of irq_sticky failed.
ERROR: AXI-Lite write channel was not ready for CMD write.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: kick_pulse did not assert on CMD write.
ERROR: kick_pulse lasted longer than one cycle.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: CMD register should read as zero. Got 00000001
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write channel was not ready in idle state.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_224416_826723_5f6af1__sample_6
generated.v preview 
module axil_sensor_csr (
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output reg awready = 0,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output reg wready = 0,
    output reg [1:0] bresp = 2'b00,
    output reg bvalid = 0,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output reg arready = 0,
    output reg [31:0] rdata = 32'd0,
    output reg [1:0] rresp = 2'b00,
    output reg rvalid = 0,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output reg block_enable = 0,
    output reg [7:0] gain = 8'd0,
    output reg kick_pulse = 0,
    output reg irq_sticky = 0
);

    // Register addresses and fields
    localparam CTRL_ADDR = 8'h00;
    localparam STATUS_ADDR = 8'h04;
    localparam CMD_ADDR = 8'h08;
...
functional details 
[stdout]
ERROR: reset values are incorrect.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL bit 0 failed.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: STATUS read without IRQ bit set returned wrong value. Got 0000005c
ERROR: irq_evt did not set irq_sticky.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: STATUS read with IRQ bit set returned wrong value. Got 0000015c
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: writing 0 incorrectly cleared irq_sticky.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready for CMD write.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: kick_pulse did not assert on CMD write.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: CMD register should read as zero. Got 00000001
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_224416_826723_5f6af1__sample_7
generated.v preview 
module axil_sensor_csr (
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output reg awready = 0,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output reg wready = 0,
    output reg [1:0] bresp = 2'b00,
    output reg bvalid = 0,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output reg arready = 0,
    output reg [31:0] rdata = 32'd0,
    output reg [1:0] rresp = 2'b00,
    output reg rvalid = 0,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output reg block_enable = 0,
    output reg [7:0] gain = 8'd0,
    output reg kick_pulse = 0,
    output reg irq_sticky = 0
);

    // Register addresses and fields
    localparam CTRL_ADDR   = 8'h00;
    localparam STATUS_ADDR = 8'h04;
    localparam CMD_ADDR    = 8'h08;
...
functional details 
[stdout]
ERROR: reset values are incorrect.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL bit 0 failed.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: STATUS read without IRQ bit set returned wrong value. Got 0000005c
ERROR: irq_evt did not set irq_sticky.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: STATUS read with IRQ bit set returned wrong value. Got 0000005c
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: writing 0 incorrectly cleared irq_sticky.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready for CMD write.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: kick_pulse did not assert on CMD write.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: CMD register should read as zero. Got 00000001
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_224416_826723_5f6af1 ok failed failed skipped failed syntax /data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:23: error: block_enable Unable to assign to unresolved wires.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_224416_826723_5f6af1__sample_8
generated.v preview 
module axil_sensor_csr (
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output reg awready = 0,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output reg wready = 0,
    output reg [1:0] bresp = 2'b00,
    output reg bvalid = 0,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output reg arready = 0,
    output reg [31:0] rdata = 32'd0,
    output reg [1:0] rresp = 2'b00,
    output reg rvalid = 0,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output reg block_enable = 0,
    output reg [7:0] gain = 8'd0,
    output reg kick_pulse = 0,
    output reg irq_sticky = 0
);

    // Register addresses
    localparam CTRL_ADDR = 8'h00;
    localparam STATUS_ADDR = 8'h04;
    localparam CMD_ADDR = 8'h08;
...
syntax details 
[stderr]
/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:23: error: block_enable Unable to assign to unresolved wires.
/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:24: error: gain Unable to assign to unresolved wires.
/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:26: error: irq_sticky Unable to assign to unresolved wires.
Elaboration failed
functional details 
[stderr]
/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:23: error: block_enable Unable to assign to unresolved wires.
/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:24: error: gain Unable to assign to unresolved wires.
/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:26: error: irq_sticky Unable to assign to unresolved wires.
3 error(s) during elaboration.
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:23: error: block_enable Unable to assign to unresolved wires.\n/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:24: error: gain Unable to assign to unresolved wires.\n/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_8/generated.v:26: error: irq_sticky Unable to assign to unresolved wires.\nElaboration failed\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:23: error: block_enable Unable to assign to unresolved wires.\n/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:24: error: gain Unable to assign to unresolved wires.\n/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/pashencev__07_csr_register_map_generation__task_72/sample_8/functional/generated.v:26: error: irq_sticky Unable to assign to unresolved wires.\n3 error(s) during elaboration.\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write channel was not ready in idle state.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_224416_826723_5f6af1__sample_9
generated.v preview 
module axil_sensor_csr (
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output reg awready = 0,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output reg wready = 0,
    output reg [1:0] bresp = 2'b00,
    output reg bvalid = 0,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output reg arready = 0,
    output reg [31:0] rdata = 0,
    output reg [1:0] rresp = 2'b00,
    output reg rvalid = 0,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output reg block_enable = 0,
    output reg [7:0] gain = 8,
    output reg kick_pulse = 0,
    output reg irq_sticky = 0
);

    // Register addresses
    localparam CTRL_ADDR = 8'h00;
    localparam STATUS_ADDR = 8'h04;
    localparam CMD_ADDR = 8'h08;
...
functional details 
[stdout]
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL bit 0 failed.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000
ERROR: irq_evt did not set irq_sticky.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000000
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: writing 0 incorrectly cleared irq_sticky.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready for CMD write.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: kick_pulse did not assert on CMD write.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: CMD register should read as zero. Got 00000001
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write channel was not ready in idle state.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_224416_826723_5f6af1 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_224416_826723_5f6af1__sample_10
generated.v preview 
module axil_sensor_csr (
    input clk,
    input rst_n,
    input [7:0] awaddr,
    input awvalid,
    output reg awready = 0,
    input [31:0] wdata,
    input [3:0] wstrb,
    input wvalid,
    output reg wready = 0,
    output reg [1:0] bresp = 2'b00,
    output reg bvalid = 0,
    input bready,
    input [7:0] araddr,
    input arvalid,
    output reg arready = 0,
    output reg [31:0] rdata = 32'd0,
    output reg [1:0] rresp = 2'b00,
    output reg rvalid = 0,
    input rready,
    input [7:0] hw_level,
    input irq_evt,
    output reg block_enable = 0,
    output reg [7:0] gain = 8'd0,
    output reg kick_pulse = 0,
    output reg irq_sticky = 0
);

    // Register addresses and fields
    localparam CTRL_ADDR = 8'h00;
    localparam STATUS_ADDR = 8'h04;
    localparam CMD_ADDR = 8'h08;
...
functional details 
[stdout]
ERROR: reset values are incorrect.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL bit 0 failed.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000
ERROR: irq_evt did not set irq_sticky.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: STATUS read with IRQ bit set returned wrong value. Got 00000001
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: writing 0 incorrectly cleared irq_sticky.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready for CMD write.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: kick_pulse did not assert on CMD write.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: CMD register should read as zero. Got 00000001
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: reset values are incorrect.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}