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deepseek-coder-v2:16b | RAG on

13_rtllm_arithmetic / task_02 | verified_adder_16bit

benchmarkrtllm
task_idrtllm/13_rtllm_arithmetic/task_02
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260426_224416_826723_5f6af1

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_224416_826723_5f6af1 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_224416_826723_5f6af1__sample_1
generated.v preview 
module verified_adder_16bit (
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [14:0] carries;

    adder_8bit u0 (a[7:0], b[7:0], Cin, y[7:0], carries[0]);
    adder_8bit u1 (a[15:8], b[15:8], carries[0], y[15:8], carries[1]);

    assign Co = carries[1];
endmodule

module adder_8bit (
    input  [7:0] a,
    input  [7:0] b,
    input        Cin,
    output [7:0] y,
    output       Co
);

    wire [6:0] carries;

    full_adder u0 (a[0], b[0], Cin, y[0], carries[0]);
    full_adder u1 (a[1], b[1], carries[0], y[1], carries[1]);
    full_adder u2 (a[2], b[2], carries[1], y[2], carries[2]);
    full_adder u3 (a[3], b[3], carries[2], y[3], carries[3]);
    full_adder u4 (a[4], b[4], carries[3], y[4], carries[4]);
    full_adder u5 (a[5], b[5], carries[4], y[5], carries[5]);
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_224416_826723_5f6af1 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_224416_826723_5f6af1__sample_2
generated.v preview 
module verified_adder_16bit (
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [14:0] carry;

    adder_8bit u0 (a[7:0], b[7:0], Cin, y[7:0], carry[0]);
    adder_8bit u1 (a[15:8], b[15:8], carry[0], y[15:8], carry[1]);

    assign Co = carry[1];
endmodule

module adder_8bit (
    input  [7:0] a,
    input  [7:0] b,
    input        Cin,
    output [7:0] y,
    output       Co
);

    wire [6:0] carry;

    full_adder u0 (a[0], b[0], Cin, y[0], carry[0]);
    full_adder u1 (a[1], b[1], carry[0], y[1], carry[1]);
    full_adder u2 (a[2], b[2], carry[1], y[2], carry[2]);
    full_adder u3 (a[3], b[3], carry[2], y[3], carry[3]);
    full_adder u4 (a[4], b[4], carry[3], y[4], carry[4]);
    full_adder u5 (a[5], b[5], carry[4], y[5], carry[5]);
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_224416_826723_5f6af1 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_224416_826723_5f6af1__sample_3
generated.v preview 
module verified_adder_16bit (
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [14:0] carry;

    adder_8bit u0 (a[7:0], b[7:0], Cin, y[7:0], carry[0]);
    adder_8bit u1 (a[15:8], b[15:8], carry[0], y[15:8], carry[1]);

    assign Co = carry[1];
endmodule

module adder_8bit (
    input  [7:0] a,
    input  [7:0] b,
    input        Cin,
    output [7:0] y,
    output       Co
);

    wire [6:0] carry;

    full_adder u0 (a[0], b[0], Cin, y[0], carry[0]);
    full_adder u1 (a[1], b[1], carry[0], y[1], carry[1]);
    full_adder u2 (a[2], b[2], carry[1], y[2], carry[2]);
    full_adder u3 (a[3], b[3], carry[2], y[3], carry[3]);
    full_adder u4 (a[4], b[4], carry[3], y[4], carry[4]);
    full_adder u5 (a[5], b[5], carry[4], y[5], carry[5]);
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_224416_826723_5f6af1 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_224416_826723_5f6af1__sample_4
generated.v preview 
module verified_adder_16bit (
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [14:0] carry;

    adder_8bit u0 (a[7:0], b[7:0], Cin, y[7:0], carry[0]);
    adder_8bit u1 (a[15:8], b[15:8], carry[0], y[15:8], carry[1]);

    assign Co = carry[1];
endmodule

module adder_8bit (
    input  [7:0] a,
    input  [7:0] b,
    input        Cin,
    output [7:0] y,
    output       Co
);

    wire [6:0] carry;

    full_adder u0 (a[0], b[0], Cin, y[0], carry[0]);
    full_adder u1 (a[1], b[1], carry[0], y[1], carry[1]);
    full_adder u2 (a[2], b[2], carry[1], y[2], carry[2]);
    full_adder u3 (a[3], b[3], carry[2], y[3], carry[3]);
    full_adder u4 (a[4], b[4], carry[3], y[4], carry[4]);
    full_adder u5 (a[5], b[5], carry[4], y[5], carry[5]);
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_224416_826723_5f6af1 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_224416_826723_5f6af1__sample_5
generated.v preview 
module verified_adder_16bit (
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [14:0] carry;

    adder_8bit u0 (a[7:0], b[7:0], Cin, y[7:0], carry[0]);
    adder_8bit u1 (a[15:8], b[15:8], carry[0], y[15:8], carry[1]);

    assign Co = carry[1];
endmodule

module adder_8bit (
    input  [7:0] a,
    input  [7:0] b,
    input        Cin,
    output [7:0] y,
    output       Co
);

    wire [6:0] carry;

    full_adder u0 (a[0], b[0], Cin, y[0], carry[0]);
    full_adder u1 (a[1], b[1], carry[0], y[1], carry[1]);
    full_adder u2 (a[2], b[2], carry[1], y[2], carry[2]);
    full_adder u3 (a[3], b[3], carry[2], y[3], carry[3]);
    full_adder u4 (a[4], b[4], carry[3], y[4], carry[4]);
    full_adder u5 (a[5], b[5], carry[4], y[5], carry[5]);
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_224416_826723_5f6af1 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_224416_826723_5f6af1__sample_6
generated.v preview 
module verified_adder_16bit (
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [14:0] carry;

    adder_8bit u0 (a[7:0], b[7:0], Cin, y[7:0], carry[0]);
    adder_8bit u1 (a[15:8], b[15:8], carry[0], y[15:8], carry[1]);

    assign Co = carry[1];
endmodule

module adder_8bit (
    input  [7:0] a,
    input  [7:0] b,
    input        Cin,
    output [7:0] y,
    output       Co
);

    wire [6:0] carry;

    full_adder u0 (a[0], b[0], Cin, y[0], carry[0]);
    full_adder u1 (a[1], b[1], carry[0], y[1], carry[1]);
    full_adder u2 (a[2], b[2], carry[1], y[2], carry[2]);
    full_adder u3 (a[3], b[3], carry[2], y[3], carry[3]);
    full_adder u4 (a[4], b[4], carry[3], y[4], carry[4]);
    full_adder u5 (a[5], b[5], carry[4], y[5], carry[5]);
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_224416_826723_5f6af1 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_224416_826723_5f6af1__sample_7
generated.v preview 
module verified_adder_16bit (
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [14:0] carry;

    adder_8bit u0 (a[7:0], b[7:0], Cin, y[7:0], carry[0]);
    adder_8bit u1 (a[15:8], b[15:8], carry[0], y[15:8], carry[1]);

    assign Co = carry[1];
endmodule

module adder_8bit (
    input  [7:0] a,
    input  [7:0] b,
    input        Cin,
    output [7:0] y,
    output       Co
);

    wire [6:0] carry;

    full_adder u0 (a[0], b[0], Cin, y[0], carry[0]);
    full_adder u1 (a[1], b[1], carry[0], y[1], carry[1]);
    full_adder u2 (a[2], b[2], carry[1], y[2], carry[2]);
    full_adder u3 (a[3], b[3], carry[2], y[3], carry[3]);
    full_adder u4 (a[4], b[4], carry[3], y[4], carry[4]);
    full_adder u5 (a[5], b[5], carry[4], y[5], carry[5]);
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_224416_826723_5f6af1 ok failed failed skipped failed syntax /data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/generated.v:39: error: 'full_adder' has already been declared in this scope.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_224416_826723_5f6af1__sample_8
generated.v preview 
module full_adder(
    input  wire [15:0] a,
    input  wire [15:0] b,
    input  wire        Cin,
    output wire [15:0] y,
    output wire        Co
);

wire [14:0] carry;

adder_8bit u0(a[7:0], b[7:0], Cin, y[7:0], carry[0]);
adder_8bit u1(a[15:8], b[15:8], carry[0], y[15:8], carry[1]);

assign Co = carry[1];

endmodule

module adder_8bit(
    input  wire [7:0] a,
    input  wire [7:0] b,
    input  wire       Cin,
    output wire [7:0] y,
    output wire       Co
);

wire [6:0] carry;

full_adder u2(a[0], b[0], Cin, y[0], carry[0]);
full_adder u3(a[1], b[1], carry[0], y[1], carry[1]);
full_adder u4(a[2], b[2], carry[1], y[2], carry[2]);
full_adder u5(a[3], b[3], carry[2], y[3], carry[3]);
full_adder u6(a[4], b[4], carry[3], y[4], carry[4]);
...
syntax details 
[stderr]
/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/generated.v:39: error: 'full_adder' has already been declared in this scope.
/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/generated.v:1:      : It was declared here as a module.
/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/generated.v:50: error: Module full_adder was already declared here: /data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/generated.v:1
functional details 
[stderr]
/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/functional/generated.v:39: error: 'full_adder' has already been declared in this scope.
/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/functional/generated.v:1:      : It was declared here as a module.
/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/functional/generated.v:50: error: Module full_adder was already declared here: /data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/functional/generated.v:1
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "syntax",
    "code": "syntax.iverilog_failed",
    "message": "/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/generated.v:39: error: 'full_adder' has already been declared in this scope.\n/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/generated.v:1:      : It was declared here as a module.\n/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/generated.v:50: error: Module full_adder was already declared here: /data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/generated.v:1\n\n",
    "retryable": false,
    "details": {}
  },
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/functional/generated.v:39: error: 'full_adder' has already been declared in this scope.\n/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/functional/generated.v:1:      : It was declared here as a module.\n/data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/functional/generated.v:50: error: Module full_adder was already declared here: /data/eval/out/run_20260426_224416_826723_5f6af1/tmp/deepseek_coder_v2/rtllm__13_rtllm_arithmetic__task_02/sample_8/functional/generated.v:1\n\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": false,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_224416_826723_5f6af1 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_224416_826723_5f6af1__sample_9
generated.v preview 
module verified_adder_16bit (
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [14:0] carry;

    adder_8bit u0 (a[7:0], b[7:0], Cin, y[7:0], carry[0]);
    adder_8bit u1 (a[15:8], b[15:8], carry[0], y[15:8], carry[1]);

    assign Co = carry[1];
endmodule

module adder_8bit (
    input  [7:0] a,
    input  [7:0] b,
    input        Cin,
    output [7:0] y,
    output       Co
);

    wire [6:0] carry;

    full_adder u0 (a[0], b[0], Cin, y[0], carry[0]);
    full_adder u1 (a[1], b[1], carry[0], y[1], carry[1]);
    full_adder u2 (a[2], b[2], carry[1], y[2], carry[2]);
    full_adder u3 (a[3], b[3], carry[2], y[3], carry[3]);
    full_adder u4 (a[4], b[4], carry[3], y[4], carry[4]);
    full_adder u5 (a[5], b[5], carry[4], y[5], carry[5]);
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_224416_826723_5f6af1 ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_224416_826723_5f6af1__sample_10
generated.v preview 
module verified_adder_16bit (
    input  [15:0] a,
    input  [15:0] b,
    input         Cin,
    output [15:0] y,
    output        Co
);

    wire [14:0] carry;

    adder_8bit u0 (a[7:0], b[7:0], Cin, y[7:0], carry[0]);
    adder_8bit u1 (a[15:8], b[15:8], carry[0], y[15:8], carry[1]);

    assign Co = carry[1];
endmodule

module adder_8bit (
    input  [7:0] a,
    input  [7:0] b,
    input        Cin,
    output [7:0] y,
    output       Co
);

    wire [6:0] carry;

    full_adder u0 (a[0], b[0], Cin, y[0], carry[0]);
    full_adder u1 (a[1], b[1], carry[0], y[1], carry[1]);
    full_adder u2 (a[2], b[2], carry[1], y[2], carry[2]);
    full_adder u3 (a[3], b[3], carry[2], y[3], carry[3]);
    full_adder u4 (a[4], b[4], carry[3], y[4], carry[4]);
    full_adder u5 (a[5], b[5], carry[4], y[5], carry[5]);
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_16bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_16bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}