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deepseek-coder-v2:16b | RAG on

13_rtllm_arithmetic / task_10 | verified_radix2_div

benchmarkrtllm
task_idrtllm/13_rtllm_arithmetic/task_10
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples80.0%
synth_pass_rate_samples0.0%
source_runsrun_20260426_224416_826723_5f6af1

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_224416_826723_5f6af1 ok ok failed skipped failed functional error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_224416_826723_5f6af1__sample_1
generated.v preview 
module radix2_div (
    input clk,
    input rst,
    input sign,
    input [7:0] dividend,
    input [7:0] divisor,
    input opn_valid,
    input res_ready,
    output reg res_valid,
    output reg [15:0] result
);

reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg neg_divisor;
reg start_cnt;
reg [3:0] cnt;
reg [15:0] sr;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        res_valid <= 0;
        cnt <= 0;
        start_cnt <= 0;
        sr <= 0;
    end else if (opn_valid && !res_valid) begin
        abs_dividend = dividend;
        abs_divisor = divisor;
        neg_divisor = 0;
        if (sign == 1'b1 && dividend[7] == 1'b1) abs_dividend = -dividend;
        if (sign == 1'b1 && divisor[7] == 1'b1) begin
            abs_divisor = -divisor;
...
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_error",
    "message": "error",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_224416_826723_5f6af1 ok ok ok failed failed synthesis OpenLane failed: 2
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_224416_826723_5f6af1__sample_2
generated.v preview 
module radix2_div (
    input wire clk,
    input wire rst,
    input wire sign,
    input wire [7:0] dividend,
    input wire [7:0] divisor,
    input wire opn_valid,
    input wire res_ready,
    output reg res_valid,
    output reg [15:0] result
);

reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] sr;
reg [2:0] cnt;
reg start_cnt;
reg neg_divisor;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        res_valid <= 0;
        cnt <= 0;
        start_cnt <= 0;
    end else if (opn_valid && !res_valid) begin
        abs_dividend = dividend[7] ? -dividend : dividend;
        abs_divisor = divisor[7] ? -divisor : divisor;
        neg_divisor = divisor[7] ? 1'b1 : 1'b0;
        sr <= {abs_dividend, 8'b0};
        cnt <= 1;
        start_cnt <= 1;
    end else if (start_cnt) begin
...
functional details 
[stdout]
Error: dividend=100, divisor= 10, expected=000a, got=f600
Error: dividend=156, divisor= 10, expected=00f6, got=f600
Error: dividend=100, divisor=246, expected=00f6, got=f600
Error: dividend=156, divisor=246, expected=000a, got=f600
Error: dividend=123, divisor=123, expected=0001, got=f600
Error: dividend=  0, divisor=123, expected=0000, got=f600
Error: dividend=123, divisor=251, expected=7b00, got=f600
Error: dividend=255, divisor=  7, expected=0324, got=f600
===========Failed===========          8
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 325000 (1ps)
synthesis details 
[error]
OpenLane failed: 2
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.failed",
    "message": "OpenLane failed: 2",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_224416_826723_5f6af1 ok ok ok failed failed synthesis OpenLane failed: 2
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_224416_826723_5f6af1__sample_3
generated.v preview 
module radix2_div (
    input clk,
    input rst,
    input sign,
    input [7:0] dividend,
    input [7:0] divisor,
    input opn_valid,
    input res_ready,
    output reg res_valid,
    output reg [15:0] result
);

reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg neg_divisor;
reg start_cnt;
reg [3:0] cnt;
reg [15:0] sr;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        res_valid <= 0;
        cnt <= 0;
        start_cnt <= 0;
        sr <= 0;
    end else if (opn_valid && !res_valid) begin
        abs_dividend <= dividend;
        abs_divisor <= divisor;
        neg_divisor <= sign ? divisor[7] : 1'b0;
        if (sign && divisor[7]) abs_divisor = -divisor;
        sr <= {abs_dividend, 8'b0};
        cnt <= 1;
...
functional details 
[stdout]
Error: dividend=100, divisor= 10, expected=000a, got=0000
Error: dividend=156, divisor= 10, expected=00f6, got=0000
Error: dividend=100, divisor=246, expected=00f6, got=0000
Error: dividend=156, divisor=246, expected=000a, got=0000
Error: dividend=123, divisor=123, expected=0001, got=0000
Error: dividend=123, divisor=251, expected=7b00, got=0000
Error: dividend=255, divisor=  7, expected=0324, got=0000
===========Failed===========          7
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 825000 (1ps)
synthesis details 
[error]
OpenLane failed: 2
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.failed",
    "message": "OpenLane failed: 2",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_224416_826723_5f6af1 ok ok ok failed failed synthesis OpenLane failed: 2
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_224416_826723_5f6af1__sample_4
generated.v preview 
module radix2_div (
    input clk,
    input rst,
    input sign,
    input [7:0] dividend,
    input [7:0] divisor,
    input opn_valid,
    input res_ready,
    output reg res_valid,
    output reg [15:0] result
);

reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg neg_divisor;
reg start_cnt;
reg [3:0] cnt;
reg [15:0] sr;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        res_valid <= 0;
        cnt <= 0;
        start_cnt <= 0;
        sr <= 0;
    end else if (opn_valid && !res_valid) begin
        abs_dividend <= dividend;
        abs_divisor <= divisor;
        neg_divisor <= sign ? divisor[7] : 1'b0;
        if (sign && divisor[7]) abs_divisor = -divisor;
        sr <= {abs_dividend, 8'b0};
        cnt <= 1;
...
functional details 
[stdout]
Error: dividend=100, divisor= 10, expected=000a, got=0000
Error: dividend=156, divisor= 10, expected=00f6, got=0000
Error: dividend=100, divisor=246, expected=00f6, got=0000
Error: dividend=156, divisor=246, expected=000a, got=0000
Error: dividend=123, divisor=123, expected=0001, got=0000
Error: dividend=123, divisor=251, expected=7b00, got=0000
Error: dividend=255, divisor=  7, expected=0324, got=0000
===========Failed===========          7
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 825000 (1ps)
synthesis details 
[error]
OpenLane failed: 2
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.failed",
    "message": "OpenLane failed: 2",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_224416_826723_5f6af1 ok ok ok failed failed synthesis OpenLane failed: 2
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_224416_826723_5f6af1__sample_5
generated.v preview 
module radix2_div (
    input wire clk,
    input wire rst,
    input wire sign,
    input wire [7:0] dividend,
    input wire [7:0] divisor,
    input wire opn_valid,
    input wire res_ready,
    output reg res_valid,
    output reg [15:0] result
);

reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] sr;
reg [2:0] cnt;
reg start_cnt;
reg neg_divisor;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        res_valid <= 0;
        cnt <= 0;
        start_cnt <= 0;
    end else if (opn_valid && !res_valid) begin
        abs_dividend = dividend[7] ? -dividend : dividend;
        abs_divisor = divisor[7] ? -divisor : divisor;
        neg_divisor = divisor[7] ? 1'b1 : 1'b0;
        sr = {abs_dividend, 1'b0};
        cnt <= 3'd1;
        start_cnt <= 1'b1;
    end else if (start_cnt) begin
...
functional details 
[stdout]
Error: dividend=100, divisor= 10, expected=000a, got=0500
Error: dividend=156, divisor= 10, expected=00f6, got=0500
Error: dividend=100, divisor=246, expected=00f6, got=0500
Error: dividend=156, divisor=246, expected=000a, got=0500
Error: dividend=123, divisor=123, expected=0001, got=0fb8
Error: dividend=  0, divisor=123, expected=0000, got=3139
Error: dividend=123, divisor=251, expected=7b00, got=3980
Error: dividend=255, divisor=  7, expected=0324, got=1901
===========Failed===========          8
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 745000 (1ps)
synthesis details 
[error]
OpenLane failed: 2
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.failed",
    "message": "OpenLane failed: 2",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_224416_826723_5f6af1 ok ok ok failed failed synthesis OpenLane failed: 2
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_224416_826723_5f6af1__sample_6
generated.v preview 
module radix2_div (
    input wire clk,
    input wire rst,
    input wire sign,
    input wire [7:0] dividend,
    input wire [7:0] divisor,
    input wire opn_valid,
    input wire res_ready,
    output reg res_valid,
    output reg [15:0] result
);

reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] sr;
reg [2:0] cnt;
reg start_cnt;
reg neg_divisor;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        res_valid <= 0;
        cnt <= 0;
        start_cnt <= 0;
    end else if (opn_valid && !res_valid) begin
        abs_dividend = dividend[7] ? -dividend : dividend;
        abs_divisor = divisor[7] ? -divisor : divisor;
        neg_divisor = divisor[7] ? 1'b1 : 1'b0;
        sr = {abs_dividend, 1'b0};
        cnt <= 3'd1;
        start_cnt <= 1'b1;
    end else if (start_cnt) begin
...
functional details 
[stdout]
Error: dividend=100, divisor= 10, expected=000a, got=0500
Error: dividend=156, divisor= 10, expected=00f6, got=0500
Error: dividend=100, divisor=246, expected=00f6, got=0500
Error: dividend=156, divisor=246, expected=000a, got=0500
Error: dividend=123, divisor=123, expected=0001, got=0500
Error: dividend=  0, divisor=123, expected=0000, got=0500
Error: dividend=123, divisor=251, expected=7b00, got=0500
Error: dividend=255, divisor=  7, expected=0324, got=0500
===========Failed===========          8
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 325000 (1ps)
synthesis details 
[error]
OpenLane failed: 2
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.failed",
    "message": "OpenLane failed: 2",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260426_224416_826723_5f6af1 ok ok ok failed failed synthesis OpenLane failed: 2
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_224416_826723_5f6af1__sample_7
generated.v preview 
module radix2_div (
    input wire clk,
    input wire rst,
    input wire sign,
    input wire [7:0] dividend,
    input wire [7:0] divisor,
    input wire opn_valid,
    input wire res_ready,
    output reg res_valid,
    output reg [15:0] result
);

reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] sr;
reg [2:0] cnt;
reg start_cnt;
reg neg_divisor;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        res_valid <= 0;
        cnt <= 0;
        start_cnt <= 0;
    end else if (opn_valid && !res_valid) begin
        abs_dividend = dividend[7] ? -dividend : dividend;
        abs_divisor = divisor[7] ? -divisor : divisor;
        neg_divisor = divisor[7];
        sr = {abs_dividend, 1'b0};
        cnt <= 0;
        start_cnt <= 1;
    end else if (start_cnt) begin
...
functional details 
[stdout]
Error: dividend=100, divisor= 10, expected=000a, got=bef0
Error: dividend=156, divisor= 10, expected=00f6, got=bef0
Error: dividend=100, divisor=246, expected=00f6, got=bef0
Error: dividend=156, divisor=246, expected=000a, got=bef0
Error: dividend=123, divisor=123, expected=0001, got=bef0
Error: dividend=  0, divisor=123, expected=0000, got=bef0
Error: dividend=123, divisor=251, expected=7b00, got=bef0
Error: dividend=255, divisor=  7, expected=0324, got=bef0
===========Failed===========          8
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 335000 (1ps)
synthesis details 
[error]
OpenLane failed: 2
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.failed",
    "message": "OpenLane failed: 2",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_224416_826723_5f6af1 ok ok ok failed failed synthesis OpenLane failed: 2
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_224416_826723_5f6af1__sample_8
generated.v preview 
module radix2_div (
    input wire clk,
    input wire rst,
    input wire sign,
    input wire [7:0] dividend,
    input wire [7:0] divisor,
    input wire opn_valid,
    input wire res_ready,
    output reg res_valid,
    output reg [15:0] result
);

reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] sr;
reg [2:0] cnt;
reg start_cnt;
reg neg_divisor;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        res_valid <= 0;
        cnt <= 0;
        start_cnt <= 0;
    end else if (opn_valid && !res_valid) begin
        abs_dividend = dividend[7] ? -dividend : dividend;
        abs_divisor = divisor[7] ? -divisor : divisor;
        neg_divisor = divisor[7] ? 1'b1 : 1'b0;
        sr = {abs_dividend, 1'b0};
        cnt <= 3'd1;
        start_cnt <= 1'b1;
    end else if (start_cnt) begin
...
functional details 
[stdout]
Error: dividend=156, divisor= 10, expected=00f6, got=000a
Error: dividend=100, divisor=246, expected=00f6, got=000a
Error: dividend=123, divisor=123, expected=0001, got=000a
Error: dividend=  0, divisor=123, expected=0000, got=000a
Error: dividend=123, divisor=251, expected=7b00, got=000a
Error: dividend=255, divisor=  7, expected=0324, got=000a
===========Failed===========          6
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 325000 (1ps)
synthesis details 
[error]
OpenLane failed: 2
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.failed",
    "message": "OpenLane failed: 2",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_224416_826723_5f6af1 ok ok failed skipped failed functional error
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_224416_826723_5f6af1__sample_9
generated.v preview 
module radix2_div (
    input clk,
    input rst,
    input sign,
    input [7:0] dividend,
    input [7:0] divisor,
    input opn_valid,
    input res_ready,
    output reg res_valid,
    output reg [15:0] result
);

reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg [15:0] sr;
reg [2:0] cnt;
reg start_cnt;
reg NEG_DIVISOR;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        res_valid <= 0;
        cnt <= 0;
        start_cnt <= 0;
    end else if (opn_valid && !res_valid) begin
        abs_dividend <= (dividend[7] & sign) ? -dividend : dividend;
        abs_divisor <= (divisor[7] & sign) ? -divisor : divisor;
        sr <= {abs_dividend, 1'b0};
        NEG_DIVISOR <= -abs_divisor;
        cnt <= 1;
        start_cnt <= 1;
    end else if (start_cnt && cnt < 8) begin
...
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_error",
    "message": "error",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260426_224416_826723_5f6af1 ok ok ok failed failed synthesis OpenLane failed: 2
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\deepseek-coder-v2-16b\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_10\samples\run_20260426_224416_826723_5f6af1__sample_10
generated.v preview 
module radix2_div (
    input clk,
    input rst,
    input sign,
    input [7:0] dividend,
    input [7:0] divisor,
    input opn_valid,
    input res_ready,
    output reg res_valid,
    output reg [15:0] result
);

reg [7:0] abs_dividend;
reg [7:0] abs_divisor;
reg neg_divisor;
reg start_cnt;
reg [3:0] cnt;
reg [15:0] sr;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        res_valid <= 0;
        cnt <= 0;
        start_cnt <= 0;
        sr <= 0;
    end else if (opn_valid && !res_valid) begin
        abs_dividend <= dividend;
        abs_divisor <= divisor;
        neg_divisor <= sign ? divisor[7] : 1'b0;
        if (sign && divisor[7]) abs_divisor = -divisor;
        sr <= {abs_dividend, 8'b0};
        cnt <= 1;
...
functional details 
[stdout]
Error: dividend=100, divisor= 10, expected=000a, got=0000
Error: dividend=156, divisor= 10, expected=00f6, got=0000
Error: dividend=100, divisor=246, expected=00f6, got=0000
Error: dividend=156, divisor=246, expected=000a, got=0000
Error: dividend=123, divisor=123, expected=0001, got=0000
Error: dividend=123, divisor=251, expected=7b00, got=0000
Error: dividend=255, divisor=  7, expected=0324, got=0000
===========Failed===========          7
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_10/tb.v:87: $finish called at 825000 (1ps)
synthesis details 
[error]
OpenLane failed: 2
errors[] 
[
  {
    "stage": "openlane",
    "code": "openlane.failed",
    "message": "OpenLane failed: 2",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}