07_csr_register_map_generation / task_71 | apb_lock_cfg
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260424_142537_441024_d248e7 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_142537_441024_d248e7__sample_1
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire [31:0] cfg_next;
wire [31:0] status_next;
wire [31:0] lock_next;
...
synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_1 | run_20260424_144121_405769_1acdc5 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_144121_405769_1acdc5__sample_1
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire wr_en;
wire rd_en;
wire [7:0] addr;
wire [31:0] cfg_next;
wire [31:0] status_next;
wire [31:0] lock_next;
...
synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_1 | run_20260424_172135_562392_bd9fc2 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_172135_562392_bd9fc2__sample_1
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire [7:0] addr;
wire [31:0] cfg_wdata;
wire cfg_write_en;
wire lock_write_en;
wire status_write_en;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_1 | run_20260424_230145_632624_082334 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_230145_632624_082334__sample_1
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire [31:0] cfg_next;
wire [31:0] status_next;
wire [31:0] lock_next;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_2 | run_20260424_142537_441024_d248e7 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_142537_441024_d248e7__sample_2
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output reg [1:0] mode,
output reg [7:0] limit,
output reg cfg_locked,
output reg fault_sticky,
output reg apply_pulse
);
assign pready = 1'b1;
wire apb_wr;
wire apb_rd;
wire sel_cfg;
wire sel_lock;
wire sel_status;
wire sel_cmd;
assign apb_wr = psel & penable & pwrite;
assign apb_rd = psel & penable & ~pwrite;
assign sel_cfg = (paddr == 8'h00);
...
synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_2 | run_20260424_144121_405769_1acdc5 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_144121_405769_1acdc5__sample_2
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire wr_cfg;
wire wr_lock;
wire wr_status;
wire wr_cmd;
...
synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_2 | run_20260424_172135_562392_bd9fc2 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_172135_562392_bd9fc2__sample_2
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire write_cfg;
wire write_lock;
wire write_status;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_2 | run_20260424_230145_632624_082334 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_230145_632624_082334__sample_2
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire wr_cfg;
wire wr_lock;
wire wr_status;
wire wr_cmd;
...
functional details[stdout] ERROR: CFG partial writes failed. ERROR: CFG changed even though cfg_locked was asserted. TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260424_142537_441024_d248e7 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_142537_441024_d248e7__sample_3
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire [31:0] cfg_next;
wire [31:0] status_next;
wire [31:0] lock_next;
...
synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_3 | run_20260424_144121_405769_1acdc5 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_144121_405769_1acdc5__sample_3
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire wr_cfg;
wire wr_lock;
wire wr_status;
...
synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_3 | run_20260424_172135_562392_bd9fc2 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_172135_562392_bd9fc2__sample_3
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output reg [1:0] mode,
output reg [7:0] limit,
output reg cfg_locked,
output reg fault_sticky,
output reg apply_pulse
);
wire apb_access;
wire apb_write;
wire apb_read;
wire wr_cfg;
wire wr_lock;
wire wr_status;
wire wr_cmd;
reg [1:0] mode_n;
reg [7:0] limit_n;
reg cfg_locked_n;
reg fault_sticky_n;
reg apply_pulse_n;
...
functional details[stdout] ERROR: CFG partial writes failed. ERROR: CFG changed even though cfg_locked was asserted. TEST_FAILED /workspace/banchmarks/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260424_230145_632624_082334 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_230145_632624_082334__sample_3
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire [31:0] cfg_next;
wire [31:0] cfg_mask;
wire [31:0] cfg_wdata;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_4 | run_20260424_172135_562392_bd9fc2 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_172135_562392_bd9fc2__sample_4
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire cfg_write_en;
wire lock_write_en;
wire status_write_en;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_4 | run_20260424_230145_632624_082334 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_230145_632624_082334__sample_4
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire [31:0] cfg_wdata;
wire cfg_write_en;
wire lock_write_en;
...
functional details[stdout] ERROR: CFG partial writes failed. ERROR: CFG changed even though cfg_locked was asserted. TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260424_172135_562392_bd9fc2 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_172135_562392_bd9fc2__sample_5
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire write_cfg;
wire write_lock;
wire write_status;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_5 | run_20260424_230145_632624_082334 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_230145_632624_082334__sample_5
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire cfg_wr_en;
wire lock_wr_en;
wire status_wr_en;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_6 | run_20260424_172135_562392_bd9fc2 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_172135_562392_bd9fc2__sample_6
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire wr_en;
wire rd_en;
wire [7:0] addr;
wire [31:0] cfg_next;
wire [31:0] cfg_mask;
wire [31:0] cfg_wdata;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_6 | run_20260424_230145_632624_082334 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_230145_632624_082334__sample_6
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire [31:0] cfg_next;
wire [31:0] cfg_mask;
wire [31:0] cfg_wdata;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_7 | run_20260424_172135_562392_bd9fc2 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_172135_562392_bd9fc2__sample_7
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire [31:0] cfg_next;
wire [31:0] cfg_mask;
wire [31:0] cfg_wdata;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_7 | run_20260424_230145_632624_082334 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_230145_632624_082334__sample_7
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire wr_en;
wire rd_en;
wire [7:0] addr;
wire [31:0] cfg_next;
wire [31:0] cfg_mask;
wire [31:0] cfg_wdata;
...
functional details[stdout] ERROR: CFG partial writes failed. ERROR: CFG changed even though cfg_locked was asserted. TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260424_172135_562392_bd9fc2 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_172135_562392_bd9fc2__sample_8
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire wr_cfg;
wire wr_lock;
wire wr_status;
wire wr_cmd;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_8 | run_20260424_230145_632624_082334 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_230145_632624_082334__sample_8
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire wr_cfg;
wire wr_lock;
wire wr_status;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_9 | run_20260424_172135_562392_bd9fc2 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_172135_562392_bd9fc2__sample_9
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire cfg_write;
wire lock_write;
wire status_write;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_9 | run_20260424_230145_632624_082334 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_230145_632624_082334__sample_9
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire write_cfg;
wire write_lock;
wire write_status;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_10 | run_20260424_172135_562392_bd9fc2 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_172135_562392_bd9fc2__sample_10
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire [31:0] cfg_next;
wire [31:0] cfg_cur;
wire [31:0] status_cur;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_10 | run_20260424_230145_632624_082334 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_71\samples\run_20260424_230145_632624_082334__sample_10
generated.v previewmodule apb_lock_cfg (
input clk,
input rst_n,
input psel,
input penable,
input pwrite,
input [7:0] paddr,
input [31:0] pwdata,
input [3:0] pstrb,
output reg [31:0] prdata,
output pready,
input hw_fault_evt,
output [1:0] mode,
output [7:0] limit,
output cfg_locked,
output fault_sticky,
output apply_pulse
);
reg [1:0] mode_r;
reg [7:0] limit_r;
reg cfg_locked_r;
reg fault_sticky_r;
reg apply_pulse_r;
wire apb_access;
wire apb_write;
wire apb_read;
wire [7:0] addr;
wire [31:0] cfg_next;
wire [31:0] cfg_mask;
wire [31:0] cfg_wdata;
...
functional details[stdout] ERROR: CFG partial writes failed. ERROR: CFG changed even though cfg_locked was asserted. TEST_FAILED /workspace/banchmarks/pashencev/07_csr_register_map_generation/task_71/tb.v:180: $finish called at 206000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: CFG partial writes failed.",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|