13_rtllm_arithmetic / task_06 | verified_adder_64bit
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260424_203453_201510_6e98ce | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_1
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg en_d1;
reg en_d2;
reg [63:0] a_d1;
reg [63:0] b_d1;
reg [64:0] sum_d1;
reg [64:0] sum_d2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
en_d1 <= 1'b0;
en_d2 <= 1'b0;
a_d1 <= 64'd0;
b_d1 <= 64'd0;
sum_d1 <= 65'd0;
sum_d2 <= 65'd0;
result <= 65'd0;
o_en <= 1'b0;
end else begin
en_d1 <= i_en;
en_d2 <= en_d1;
if (i_en) begin
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_1 | run_20260424_212142_473417_af1ca5 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_212142_473417_af1ca5__sample_1
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] a_r0, b_r0;
reg [63:0] a_r1, b_r1;
reg [64:0] sum_r0;
reg [64:0] sum_r1;
reg en_r0;
reg en_r1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
a_r0 <= 64'd0;
b_r0 <= 64'd0;
a_r1 <= 64'd0;
b_r1 <= 64'd0;
sum_r0 <= 65'd0;
sum_r1 <= 65'd0;
result <= 65'd0;
en_r0 <= 1'b0;
en_r1 <= 1'b0;
o_en <= 1'b0;
end else begin
a_r0 <= adda;
b_r0 <= addb;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_1 | run_20260424_230145_632624_082334 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_1
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] a_r0, b_r0;
reg [63:0] a_r1, b_r1;
reg [64:0] sum_r0, sum_r1;
reg en_r0, en_r1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
a_r0 <= 64'd0;
b_r0 <= 64'd0;
a_r1 <= 64'd0;
b_r1 <= 64'd0;
sum_r0 <= 65'd0;
sum_r1 <= 65'd0;
result <= 65'd0;
en_r0 <= 1'b0;
en_r1 <= 1'b0;
o_en <= 1'b0;
end else begin
a_r0 <= adda;
b_r0 <= addb;
en_r0 <= i_en;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260424_203453_201510_6e98ce | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_2
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] a_r0, b_r0;
reg [63:0] a_r1, b_r1;
reg [64:0] sum_r0;
reg [64:0] sum_r1;
reg en_r0, en_r1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
a_r0 <= 64'd0;
b_r0 <= 64'd0;
a_r1 <= 64'd0;
b_r1 <= 64'd0;
sum_r0 <= 65'd0;
sum_r1 <= 65'd0;
result <= 65'd0;
en_r0 <= 1'b0;
en_r1 <= 1'b0;
o_en <= 1'b0;
end else begin
a_r0 <= adda;
b_r0 <= addb;
en_r0 <= i_en;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260424_230145_632624_082334 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_2
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg en_d1;
reg en_d2;
reg [63:0] a_d1;
reg [63:0] b_d1;
reg [64:0] sum_d1;
reg [64:0] sum_d2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
en_d1 <= 1'b0;
en_d2 <= 1'b0;
a_d1 <= 64'd0;
b_d1 <= 64'd0;
sum_d1 <= 65'd0;
sum_d2 <= 65'd0;
result <= 65'd0;
o_en <= 1'b0;
end else begin
en_d1 <= i_en;
en_d2 <= en_d1;
if (i_en) begin
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260424_203453_201510_6e98ce | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_3
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg en_d1;
reg en_d2;
reg [64:0] sum_d1;
reg [64:0] sum_d2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
en_d1 <= 1'b0;
en_d2 <= 1'b0;
sum_d1 <= 65'd0;
sum_d2 <= 65'd0;
result <= 65'd0;
o_en <= 1'b0;
end else begin
en_d1 <= i_en;
en_d2 <= en_d1;
sum_d1 <= {1'b0, adda} + {1'b0, addb};
sum_d2 <= sum_d1;
result <= sum_d2;
o_en <= en_d2;
end
end
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260424_230145_632624_082334 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_3
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_r0, addb_r0;
reg en_r0;
reg [64:0] sum_r1;
reg en_r1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
adda_r0 <= 64'd0;
addb_r0 <= 64'd0;
en_r0 <= 1'b0;
sum_r1 <= 65'd0;
en_r1 <= 1'b0;
result <= 65'd0;
o_en <= 1'b0;
end else begin
adda_r0 <= adda;
addb_r0 <= addb;
en_r0 <= i_en;
sum_r1 <= {1'b0, adda_r0} + {1'b0, addb_r0};
en_r1 <= en_r0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260424_203453_201510_6e98ce | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_4
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg en_d1;
reg en_d2;
reg [64:0] sum_d1;
reg [64:0] sum_d2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
en_d1 <= 1'b0;
en_d2 <= 1'b0;
sum_d1 <= 65'd0;
sum_d2 <= 65'd0;
result <= 65'd0;
o_en <= 1'b0;
end else begin
en_d1 <= i_en;
en_d2 <= en_d1;
if (i_en) begin
sum_d1 <= {1'b0, adda} + {1'b0, addb};
end
if (en_d1) begin
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260424_230145_632624_082334 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_4
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] a_r0, b_r0;
reg [63:0] a_r1, b_r1;
reg [64:0] sum_r0, sum_r1, sum_r2;
reg en_r0, en_r1, en_r2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
a_r0 <= 64'd0;
b_r0 <= 64'd0;
a_r1 <= 64'd0;
b_r1 <= 64'd0;
sum_r0 <= 65'd0;
sum_r1 <= 65'd0;
sum_r2 <= 65'd0;
en_r0 <= 1'b0;
en_r1 <= 1'b0;
en_r2 <= 1'b0;
result <= 65'd0;
o_en <= 1'b0;
end else begin
a_r0 <= adda;
b_r0 <= addb;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260424_203453_201510_6e98ce | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_5
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_r0, addb_r0;
reg [63:0] adda_r1, addb_r1;
reg [63:0] adda_r2, addb_r2;
reg [63:0] adda_r3, addb_r3;
reg en_r0, en_r1, en_r2, en_r3;
wire [64:0] sum0;
wire [64:0] sum1;
wire [64:0] sum2;
wire [64:0] sum3;
assign sum0 = {1'b0, adda_r0} + {1'b0, addb_r0};
assign sum1 = {1'b0, adda_r1} + {1'b0, addb_r1};
assign sum2 = {1'b0, adda_r2} + {1'b0, addb_r2};
assign sum3 = {1'b0, adda_r3} + {1'b0, addb_r3};
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
adda_r0 <= 64'b0;
addb_r0 <= 64'b0;
adda_r1 <= 64'b0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260424_230145_632624_082334 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_5
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg en_d1;
reg en_d2;
reg [64:0] sum_d1;
reg [64:0] sum_d2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
en_d1 <= 1'b0;
en_d2 <= 1'b0;
sum_d1 <= 65'd0;
sum_d2 <= 65'd0;
result <= 65'd0;
o_en <= 1'b0;
end else begin
en_d1 <= i_en;
en_d2 <= en_d1;
if (i_en)
sum_d1 <= {1'b0, adda} + {1'b0, addb};
else
sum_d1 <= 65'd0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260424_203453_201510_6e98ce | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_6
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_r0, addb_r0;
reg [63:0] adda_r1, addb_r1;
reg [63:0] sum_r0, sum_r1;
reg carry_r0, carry_r1;
reg en_r0, en_r1, en_r2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
adda_r0 <= 64'd0;
addb_r0 <= 64'd0;
adda_r1 <= 64'd0;
addb_r1 <= 64'd0;
sum_r0 <= 64'd0;
sum_r1 <= 64'd0;
carry_r0 <= 1'b0;
carry_r1 <= 1'b0;
en_r0 <= 1'b0;
en_r1 <= 1'b0;
en_r2 <= 1'b0;
result <= 65'd0;
o_en <= 1'b0;
end else begin
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260424_230145_632624_082334 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_6
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] a_r0, b_r0;
reg [63:0] a_r1, b_r1;
reg [64:0] sum_r0;
reg [64:0] sum_r1;
reg en_r0, en_r1, en_r2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
a_r0 <= 64'd0;
b_r0 <= 64'd0;
a_r1 <= 64'd0;
b_r1 <= 64'd0;
sum_r0 <= 65'd0;
sum_r1 <= 65'd0;
en_r0 <= 1'b0;
en_r1 <= 1'b0;
en_r2 <= 1'b0;
result <= 65'd0;
o_en <= 1'b0;
end else begin
en_r0 <= i_en;
en_r1 <= en_r0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260424_203453_201510_6e98ce | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_7
generated.v previewmodule verified_adder_64bit(
input clk,
input rst_n,
input i_en,
input [63:0] adda,
input [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_r0, addb_r0;
reg [63:0] adda_r1, addb_r1;
reg [63:0] adda_r2, addb_r2;
reg [63:0] adda_r3, addb_r3;
reg en_r0, en_r1, en_r2, en_r3;
reg [64:0] sum_r0, sum_r1, sum_r2, sum_r3;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
adda_r0 <= 64'd0;
addb_r0 <= 64'd0;
adda_r1 <= 64'd0;
addb_r1 <= 64'd0;
adda_r2 <= 64'd0;
addb_r2 <= 64'd0;
adda_r3 <= 64'd0;
addb_r3 <= 64'd0;
en_r0 <= 1'b0;
en_r1 <= 1'b0;
en_r2 <= 1'b0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260424_230145_632624_082334 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_7
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_r0, addb_r0;
reg [63:0] adda_r1, addb_r1;
reg [63:0] adda_r2, addb_r2;
reg [63:0] adda_r3, addb_r3;
reg en_r0, en_r1, en_r2, en_r3;
reg [64:0] sum_r0, sum_r1, sum_r2, sum_r3;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
adda_r0 <= 64'd0;
addb_r0 <= 64'd0;
adda_r1 <= 64'd0;
addb_r1 <= 64'd0;
adda_r2 <= 64'd0;
addb_r2 <= 64'd0;
adda_r3 <= 64'd0;
addb_r3 <= 64'd0;
en_r0 <= 1'b0;
en_r1 <= 1'b0;
en_r2 <= 1'b0;
en_r3 <= 1'b0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260424_203453_201510_6e98ce | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_8
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] a_r0, b_r0;
reg [63:0] a_r1, b_r1;
reg [64:0] sum_r0;
reg [64:0] sum_r1;
reg en_r0, en_r1, en_r2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
a_r0 <= 64'd0;
b_r0 <= 64'd0;
a_r1 <= 64'd0;
b_r1 <= 64'd0;
sum_r0 <= 65'd0;
sum_r1 <= 65'd0;
en_r0 <= 1'b0;
en_r1 <= 1'b0;
en_r2 <= 1'b0;
result <= 65'd0;
o_en <= 1'b0;
end else begin
en_r0 <= i_en;
en_r1 <= en_r0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260424_230145_632624_082334 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_8
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] a_r0, b_r0;
reg [63:0] a_r1, b_r1;
reg [64:0] sum_r0;
reg [64:0] sum_r1;
reg en_r0, en_r1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
a_r0 <= 64'd0;
b_r0 <= 64'd0;
a_r1 <= 64'd0;
b_r1 <= 64'd0;
sum_r0 <= 65'd0;
sum_r1 <= 65'd0;
result <= 65'd0;
en_r0 <= 1'b0;
en_r1 <= 1'b0;
o_en <= 1'b0;
end else begin
a_r0 <= adda;
b_r0 <= addb;
en_r0 <= i_en;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260424_203453_201510_6e98ce | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`. |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_9
generated.v previewmodule verified_adder_64bit (
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_r;
reg [63:0] addb_r;
reg en_r1;
reg en_r2;
reg [64:0] sum_r1;
reg [64:0] sum_r2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
adda_r <= 64'd0;
addb_r <= 64'd0;
en_r1 <= 1'b0;
en_r2 <= 1'b0;
sum_r1 <= 65'd0;
sum_r2 <= 65'd0;
result <= 65'd0;
o_en <= 1'b0;
end else begin
adda_r <= adda;
addb_r <= addb;
en_r1 <= i_en;
en_r2 <= en_r1;
...
functional details[stderr] /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`. /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`. 3 error(s) during elaboration. synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:66: error: parameter `DATA_WIDTH` not found in `tb_adder64.u_pip_add64`.\n/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:67: error: parameter `STG_WIDTH` not found in `tb_adder64.u_pip_add64`.\n3 error(s) during elaboration.\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260424_230145_632624_082334 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_9
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg en_d1;
reg en_d2;
reg [64:0] sum_d1;
reg [64:0] sum_d2;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
en_d1 <= 1'b0;
en_d2 <= 1'b0;
sum_d1 <= 65'd0;
sum_d2 <= 65'd0;
result <= 65'd0;
o_en <= 1'b0;
end else begin
en_d1 <= i_en;
en_d2 <= en_d1;
sum_d1 <= {1'b0, adda} + {1'b0, addb};
sum_d2 <= sum_d1;
result <= sum_d2;
o_en <= en_d2;
end
end
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260424_203453_201510_6e98ce | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_203453_201510_6e98ce__sample_10
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] a_r0, b_r0;
reg [63:0] a_r1, b_r1;
reg [64:0] sum_r0;
reg [64:0] sum_r1;
reg en_r0;
reg en_r1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
a_r0 <= 64'd0;
b_r0 <= 64'd0;
a_r1 <= 64'd0;
b_r1 <= 64'd0;
sum_r0 <= 65'd0;
sum_r1 <= 65'd0;
result <= 65'd0;
en_r0 <= 1'b0;
en_r1 <= 1'b0;
o_en <= 1'b0;
end else begin
en_r0 <= i_en;
en_r1 <= en_r0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260424_230145_632624_082334 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-mini\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260424_230145_632624_082334__sample_10
generated.v previewmodule verified_adder_64bit(
input wire clk,
input wire rst_n,
input wire i_en,
input wire [63:0] adda,
input wire [63:0] addb,
output reg [64:0] result,
output reg o_en
);
reg [63:0] adda_r0, addb_r0;
reg [63:0] adda_r1, addb_r1;
reg [63:0] adda_r2, addb_r2;
reg [63:0] adda_r3, addb_r3;
reg [63:0] adda_r4, addb_r4;
reg [63:0] adda_r5, addb_r5;
reg [63:0] adda_r6, addb_r6;
reg [63:0] adda_r7, addb_r7;
reg en_r0, en_r1, en_r2, en_r3, en_r4, en_r5, en_r6, en_r7;
reg [64:0] sum_r0, sum_r1, sum_r2, sum_r3, sum_r4, sum_r5, sum_r6, sum_r7;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
adda_r0 <= 64'd0; addb_r0 <= 64'd0;
adda_r1 <= 64'd0; addb_r1 <= 64'd0;
adda_r2 <= 64'd0; addb_r2 <= 64'd0;
adda_r3 <= 64'd0; addb_r3 <= 64'd0;
adda_r4 <= 64'd0; addb_r4 <= 64'd0;
adda_r5 <= 64'd0; addb_r5 <= 64'd0;
adda_r6 <= 64'd0; addb_r6 <= 64'd0;
adda_r7 <= 64'd0; addb_r7 <= 64'd0;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
adder_pipe_64bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_pipe_64bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|