13_rtllm_arithmetic / task_03 | verified_adder_32bit
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260427_102437_171676_163c0c | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_03\samples\run_20260427_102437_171676_163c0c__sample_1
generated.v previewmodule verified_adder_32bit(
input [32:1] A,
input [32:1] B,
output [32:1] S,
output C32
);
wire [16:1] A_lo, B_lo, S_lo;
wire [16:1] A_hi, B_hi, S_hi;
wire C16;
wire C32_int;
assign A_lo = A[16:1];
assign B_lo = B[16:1];
assign A_hi = A[32:17];
assign B_hi = B[32:17];
cla16 u_cla_lo(
.A(A_lo),
.B(B_lo),
.Cin(1'b0),
.S(S_lo),
.Cout(C16)
);
cla16 u_cla_hi(
.A(A_hi),
.B(B_hi),
.Cin(C16),
.S(S_hi),
.Cout(C32_int)
);
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit
3 error(s) during elaboration.
*** These modules were missing:
adder_32bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_32bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260427_102437_171676_163c0c | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_03\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v previewmodule verified_adder_32bit(
input [32:1] A,
input [32:1] B,
output [32:1] S,
output C32
);
wire [16:1] A_lo, A_hi;
wire [16:1] B_lo, B_hi;
wire [16:1] S_lo, S_hi;
wire C16;
wire C32_int;
assign A_lo = A[16:1];
assign A_hi = A[32:17];
assign B_lo = B[16:1];
assign B_hi = B[32:17];
adder_16bit_cla u_lo(
.A (A_lo),
.B (B_lo),
.Cin (1'b0),
.S (S_lo),
.Cout(C16)
);
adder_16bit_cla u_hi(
.A (A_hi),
.B (B_hi),
.Cin (C16),
.S (S_hi),
.Cout(C32_int)
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit
3 error(s) during elaboration.
*** These modules were missing:
adder_32bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_32bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260427_102437_171676_163c0c | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_03\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v previewmodule verified_adder_32bit(
input [32:1] A,
input [32:1] B,
output [32:1] S,
output C32
);
wire [16:1] A_lo, B_lo, S_lo;
wire [16:1] A_hi, B_hi, S_hi;
wire C16, C32_int;
assign A_lo = A[16:1];
assign B_lo = B[16:1];
assign A_hi = A[32:17];
assign B_hi = B[32:17];
cla_16bit u_cla_lo(
.A (A_lo),
.B (B_lo),
.Cin (1'b0),
.S (S_lo),
.Cout(C16)
);
cla_16bit u_cla_hi(
.A (A_hi),
.B (B_hi),
.Cin (C16),
.S (S_hi),
.Cout(C32_int)
);
assign S[16:1] = S_lo;
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit
3 error(s) during elaboration.
*** These modules were missing:
adder_32bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_32bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260427_102437_171676_163c0c | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_03\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v previewmodule verified_adder_32bit(
input [32:1] A,
input [32:1] B,
output [32:1] S,
output C32
);
wire [16:1] A_lo, B_lo, S_lo;
wire [16:1] A_hi, B_hi, S_hi;
wire C16;
wire C32_int;
assign A_lo = A[16:1];
assign B_lo = B[16:1];
assign A_hi = A[32:17];
assign B_hi = B[32:17];
cla_16bit u_cla_lo(
.A (A_lo),
.B (B_lo),
.Cin (1'b0),
.S (S_lo),
.Cout(C16)
);
cla_16bit u_cla_hi(
.A (A_hi),
.B (B_hi),
.Cin (C16),
.S (S_hi),
.Cout(C32_int)
);
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit
3 error(s) during elaboration.
*** These modules were missing:
adder_32bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_32bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260427_102437_171676_163c0c | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_03\samples\run_20260427_102437_171676_163c0c__sample_5
generated.v previewmodule verified_adder_32bit(
input [32:1] A,
input [32:1] B,
output [32:1] S,
output C32
);
wire [32:1] G;
wire [32:1] P;
wire [16:1] G_lo, P_lo;
wire [16:1] G_hi, P_hi;
wire [16:1] c_lo;
wire [16:1] c_hi;
wire c16;
wire c32;
genvar i;
generate
for (i = 1; i <= 32; i = i + 1) begin : gen_gp
assign G[i] = A[i] & B[i];
assign P[i] = A[i] ^ B[i];
end
endgenerate
generate
for (i = 1; i <= 16; i = i + 1) begin : gen_lo
assign G_lo[i] = G[i];
assign P_lo[i] = P[i];
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit
3 error(s) during elaboration.
*** These modules were missing:
adder_32bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_32bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260427_102437_171676_163c0c | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_03\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v previewmodule verified_adder_32bit(
input [32:1] A,
input [32:1] B,
output [32:1] S,
output C32
);
wire [16:1] A_lo, A_hi;
wire [16:1] B_lo, B_hi;
wire [16:1] S_lo, S_hi;
wire C16, C32_int;
assign A_lo = A[16:1];
assign A_hi = A[32:17];
assign B_lo = B[16:1];
assign B_hi = B[32:17];
cla16 u_cla_lo(
.A (A_lo),
.B (B_lo),
.Cin (1'b0),
.S (S_lo),
.Cout(C16)
);
cla16 u_cla_hi(
.A (A_hi),
.B (B_hi),
.Cin (C16),
.S (S_hi),
.Cout(C32_int)
);
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit
3 error(s) during elaboration.
*** These modules were missing:
adder_32bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_32bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260427_102437_171676_163c0c | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_03\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v previewmodule verified_adder_32bit(
input [32:1] A,
input [32:1] B,
output [32:1] S,
output C32
);
wire [16:1] A_lo, A_hi;
wire [16:1] B_lo, B_hi;
wire [16:1] S_lo, S_hi;
wire C16;
wire C32_int;
assign A_lo = A[16:1];
assign A_hi = A[32:17];
assign B_lo = B[16:1];
assign B_hi = B[32:17];
cla16 u_cla_lo(
.A (A_lo),
.B (B_lo),
.Cin (1'b0),
.S (S_lo),
.Cout(C16)
);
cla16 u_cla_hi(
.A (A_hi),
.B (B_hi),
.Cin (C16),
.S (S_hi),
.Cout(C32_int)
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit
3 error(s) during elaboration.
*** These modules were missing:
adder_32bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_32bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260427_102437_171676_163c0c | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_03\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v previewmodule verified_adder_32bit(
input [32:1] A,
input [32:1] B,
output [32:1] S,
output C32
);
wire [32:1] P;
wire [32:1] G;
wire [16:1] P_lo, G_lo;
wire [16:1] P_hi, G_hi;
wire [16:1] C_lo;
wire [16:1] C_hi;
wire C16;
wire C32_int;
assign P = A ^ B;
assign G = A & B;
assign P_lo = P[16:1];
assign G_lo = G[16:1];
assign P_hi = P[32:17];
assign G_hi = G[32:17];
cla16 u_cla_lo(
.P(P_lo),
.G(G_lo),
.Cin(1'b0),
.Cout(C16),
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit
3 error(s) during elaboration.
*** These modules were missing:
adder_32bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_32bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260427_102437_171676_163c0c | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_03\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v previewmodule verified_adder_32bit(
input [32:1] A,
input [32:1] B,
output [32:1] S,
output C32
);
wire [16:1] A_lo, B_lo, S_lo;
wire [16:1] A_hi, B_hi, S_hi;
wire C16, C32_int;
assign A_lo = A[16:1];
assign B_lo = B[16:1];
assign A_hi = A[32:17];
assign B_hi = B[32:17];
cla16 u_cla_lo(
.A(A_lo),
.B(B_lo),
.Cin(1'b0),
.S(S_lo),
.Cout(C16)
);
cla16 u_cla_hi(
.A(A_hi),
.B(B_hi),
.Cin(C16),
.S(S_hi),
.Cout(C32_int)
);
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit
3 error(s) during elaboration.
*** These modules were missing:
adder_32bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_32bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260427_102437_171676_163c0c | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_03\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v previewmodule verified_adder_32bit(
input [32:1] A,
input [32:1] B,
output [32:1] S,
output C32
);
wire [16:1] A_lo, B_lo, S_lo;
wire [16:1] A_hi, B_hi, S_hi;
wire C16, C32_int;
assign A_lo = A[16:1];
assign B_lo = B[16:1];
assign A_hi = A[32:17];
assign B_hi = B[32:17];
cla16 u_cla_lo(
.A (A_lo),
.B (B_lo),
.Cin (1'b0),
.S (S_lo),
.Cout(C16)
);
cla16 u_cla_hi(
.A (A_hi),
.B (B_hi),
.Cin (C16),
.S (S_hi),
.Cout(C32_int)
);
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit
3 error(s) during elaboration.
*** These modules were missing:
adder_32bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_03/tb.v:14: error: Unknown module type: adder_32bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_32bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|