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gpt-5.4-nano | RAG off

13_rtllm_arithmetic / task_06 | verified_adder_64bit

benchmarkrtllm
task_idrtllm/13_rtllm_arithmetic/task_06
samples_total10
final_success_samples0
final_success_rate_samples0.0%
functional_pass_rate_samples0.0%
synth_pass_rate_samples0.0%
source_runsrun_20260427_102437_171676_163c0c

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_1
generated.v preview 
module verified_adder_64bit (
    input              clk,
    input              rst_n,
    input              i_en,
    input      [63:0] adda,
    input      [63:0] addb,
    output reg [64:0]  result,
    output reg         o_en
);

    // Pipeline depth (several registers as requested)
    localparam integer PIPE_STAGES = 3;

    // Enable pipeline
    reg [PIPE_STAGES-1:0] en_pipe;

    // Ripple-carry adder intermediate (combinational)
    wire [64:0] sum_comb;
    wire [63:0] c; // carry into bit i (c[0] is carry into bit 0)
    assign c[0] = 1'b0;

    genvar i;
    generate
        for (i = 0; i < 63; i = i + 1) begin : gen_rca
            assign c[i+1] = (adda[i] & addb[i]) | (c[i] & (adda[i] ^ addb[i]));
        end
    endgenerate

    assign sum_comb[63:0] = (adda ^ addb) ^ {63'b0, c[63]};
    assign sum_comb[64]   = c[63] & (adda[63] ^ addb[63]) | (adda[63] & addb[63]);

    // Pipeline registers for sum
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_2
generated.v preview 
module verified_adder_64bit (
    input              clk,
    input              rst_n,
    input              i_en,
    input      [63:0] adda,
    input      [63:0] addb,
    output     [64:0] result,
    output             o_en
);

    // Pipeline depth (several stages)
    localparam integer STAGES = 3;

    // Enable pipeline
    reg [STAGES-1:0] en_pipe;

    // Ripple-carry adder combinational result
    wire [64:0] sum_comb;
    assign sum_comb = {1'b0, adda} + {1'b0, addb};

    // Pipeline registers for result
    reg [64:0] sum_pipe [0:STAGES-1];

    integer i;

    // Output assignments
    assign result = sum_pipe[STAGES-1];
    assign o_en   = en_pipe[STAGES-1];

    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_3
generated.v preview 
module verified_adder_64bit (
    input              clk,
    input              rst_n,
    input              i_en,
    input      [63:0] adda,
    input      [63:0] addb,
    output reg [64:0]  result,
    output reg         o_en
);

    // Pipeline depth (several stages)
    localparam integer STAGES = 3;

    // Enable pipeline
    reg [STAGES-1:0] en_pipe;

    // Ripple-carry adder combinational wires (full 64-bit + carry out)
    wire [63:0] sum_comb;
    wire        c_out_comb;

    // Ripple carry chain
    wire [64:0] c;
    assign c[0] = 1'b0;

    genvar i;
    generate
        for (i = 0; i < 64; i = i + 1) begin : RC
            assign {c[i+1], sum_comb[i]} = adda[i] + addb[i] + c[i];
        end
    endgenerate
    assign c_out_comb = c[64];
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_4
generated.v preview 
module verified_adder_64bit (
    input              clk,
    input              rst_n,
    input              i_en,
    input      [63:0] adda,
    input      [63:0] addb,
    output reg [64:0]  result,
    output reg         o_en
);

    // Pipeline depth (several registers)
    localparam integer STAGES = 4;

    // Enable pipeline
    reg [STAGES-1:0] en_pipe;

    // Ripple-carry adder combinational (used per stage)
    wire [64:0] sum_comb;
    wire [63:0] a = adda;
    wire [63:0] b = addb;

    wire [64:0] c;
    assign c[0] = 1'b0;

    genvar i;
    generate
        for (i = 0; i < 64; i = i + 1) begin : RC
            assign c[i+1] = (a[i] & b[i]) | (c[i] & (a[i] ^ b[i]));
        end
    endgenerate

    assign sum_comb = {c[64], (a ^ b) + (c[63:0] << 0)}; // Not used; keep synthesis-friendly
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_5
generated.v preview 
module verified_adder_64bit (
    input              clk,
    input              rst_n,
    input              i_en,
    input      [63:0] adda,
    input      [63:0] addb,
    output reg [64:0]  result,
    output reg         o_en
);

    // Pipeline depth (several stages)
    localparam integer STAGES = 4;

    // Enable pipeline
    reg [STAGES-1:0] en_pipe;

    // Ripple-carry adder combinational (64-bit + carry out)
    wire [64:0] sum_comb;
    wire [63:0] a = adda;
    wire [63:0] b = addb;

    wire [64:0] c;
    assign c[0] = 1'b0;

    genvar i;
    generate
        for (i = 0; i < 64; i = i + 1) begin : RC
            assign c[i+1] = (a[i] & b[i]) | (c[i] & (a[i] ^ b[i]));
        end
    endgenerate

    assign sum_comb = {c[64], (a ^ b) ^ c[63:0]};
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_6
generated.v preview 
module verified_adder_64bit (
    input              clk,
    input              rst_n,
    input              i_en,
    input      [63:0] adda,
    input      [63:0] addb,
    output     [64:0] result,
    output             o_en
);

    // Pipeline depth (several registers)
    localparam integer STAGES = 3;

    // Enable pipeline
    reg [STAGES-1:0] en_pipe;

    // Ripple-carry adder combinational (64-bit) with carry out
    wire [64:0] sum_comb;
    assign sum_comb = {1'b0, adda} + {1'b0, addb};

    // Pipeline registers for result
    reg [64:0] sum_pipe [0:STAGES-1];

    integer i;

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            en_pipe <= {STAGES{1'b0}};
            for (i = 0; i < STAGES; i = i + 1) begin
                sum_pipe[i] <= {65{1'b0}};
            end
        end else begin
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_7 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_7
generated.v preview 
module verified_adder_64bit (
    input  wire         clk,
    input  wire         rst_n,
    input  wire         i_en,
    input  wire [63:0]  adda,
    input  wire [63:0]  addb,
    output wire [64:0]  result,
    output wire         o_en
);

    // Pipeline depth (several registers)
    localparam integer PIPE_STAGES = 3;

    // Synchronized enable pipeline
    reg [PIPE_STAGES-1:0] en_pipe;

    // Ripple-carry adder combinational wires
    wire [64:0] sum_comb;

    // Ripple carry internal signals
    wire [63:0] c;
    assign c[0] = 1'b0;

    genvar i;
    generate
        for (i = 0; i < 63; i = i + 1) begin : gen_rca
            assign c[i+1] = (adda[i] & addb[i]) | (c[i] & (adda[i] ^ addb[i]));
        end
    endgenerate

    assign sum_comb[0]  = adda[0] ^ addb[0];
    generate
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_8
generated.v preview 
module verified_adder_64bit (
    input              clk,
    input              rst_n,
    input              i_en,
    input      [63:0] adda,
    input      [63:0] addb,
    output reg [64:0] result,
    output reg         o_en
);

    // Pipeline depth (several registers)
    localparam integer STAGES = 3;

    // Enable pipeline
    reg [STAGES-1:0] en_pipe;

    // Ripple-carry adder intermediate (combinational)
    wire [64:0] sum_comb;
    wire [63:0] a = adda;
    wire [63:0] b = addb;

    wire [63:0] c;
    assign c[0] = 1'b0;

    genvar i;
    generate
        for (i = 0; i < 63; i = i + 1) begin : RC
            assign c[i+1] = (a[i] & b[i]) | (c[i] & (a[i] ^ b[i]));
        end
    endgenerate

    wire [63:0] s;
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_9
generated.v preview 
module verified_adder_64bit (
    input              clk,
    input              rst_n,
    input              i_en,
    input      [63:0] adda,
    input      [63:0] addb,
    output reg [64:0]  result,
    output reg         o_en
);

    // Pipeline depth (several registers as requested)
    localparam integer STAGES = 3;

    // Enable pipeline
    reg [STAGES-1:0] en_pipe;

    // Ripple-carry adder combinational (computed each cycle, then pipelined)
    wire [64:0] sum_comb;
    wire [63:0] a = adda;
    wire [63:0] b = addb;

    wire [64:0] c;
    assign c[0] = 1'b0;

    genvar i;
    generate
        for (i = 0; i < 64; i = i + 1) begin : RC
            assign c[i+1] = (a[i] & b[i]) | (c[i] & (a[i] ^ b[i]));
        end
    endgenerate

    assign sum_comb[64] = c[64];
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_10 run_20260427_102437_171676_163c0c ok ok failed skipped failed functional /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_off\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_06\samples\run_20260427_102437_171676_163c0c__sample_10
generated.v preview 
module verified_adder_64bit (
    input              clk,
    input              rst_n,
    input              i_en,
    input      [63:0] adda,
    input      [63:0] addb,
    output reg [64:0]  result,
    output reg         o_en
);

    // Pipeline depth (several stages)
    localparam integer STAGES = 4;

    // Enable pipeline
    reg [STAGES-1:0] en_pipe;

    // Ripple-carry adder combinational result (full 65-bit)
    wire [64:0] sum_comb;
    assign sum_comb = {1'b0, adda} + {1'b0, addb};

    // Stage registers for sum
    reg [64:0] sum_pipe [0:STAGES-1];

    integer i;

    // Pipeline registers
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            en_pipe <= {STAGES{1'b0}};
            for (i = 0; i < STAGES; i = i + 1) begin
                sum_pipe[i] <= {65{1'b0}};
            end
...
functional details 
[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit
3 error(s) during elaboration.
*** These modules were missing:
        adder_pipe_64bit referenced 1 times.
***
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.testbench_failed",
    "message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_06/tb.v:69: error: Unknown module type: adder_pipe_64bit\n3 error(s) during elaboration.\n*** These modules were missing:\n        adder_pipe_64bit referenced 1 times.\n***\n",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}