01_ip_integration / task_11 | axi2apb_write_bridge
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__01_ip_integration__task_11\samples\run_20260426_070416_680227_376b99__sample_1
generated.v previewmodule axi2apb_write_bridge (
input clk,
input rst_n,
input [31:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
output [31:0] paddr,
output psel,
output penable,
output pwrite,
output [31:0] pwdata,
input pready,
input pslverr
);
localparam [1:0]
S_IDLE = 2'd0,
S_SETUP = 2'd1,
S_ACCESS = 2'd2,
S_RESP = 2'd3;
reg [1:0] state;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/01_ip_integration/task_11/tb.v:104: $finish called at 85000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_2 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__01_ip_integration__task_11\samples\run_20260426_070416_680227_376b99__sample_2
generated.v previewmodule axi2apb_write_bridge (
input clk,
input rst_n,
// AXI4-Lite Write Channel
input [31:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
// APB4 Master Interface
output [31:0] paddr,
output psel,
output penable,
output pwrite,
output [31:0] pwdata,
input pready,
input pslverr
);
localparam [1:0]
S_IDLE = 2'd0,
S_SETUP = 2'd1,
S_ACCESS = 2'd2,
S_RESP = 2'd3;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/01_ip_integration/task_11/tb.v:104: $finish called at 85000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_3 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__01_ip_integration__task_11\samples\run_20260426_070416_680227_376b99__sample_3
generated.v previewmodule axi2apb_write_bridge (
input clk,
input rst_n,
// AXI4-Lite Write Channel
input [31:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
// APB4 Master Interface
output [31:0] paddr,
output psel,
output penable,
output pwrite,
output [31:0] pwdata,
input pready,
input pslverr
);
localparam [1:0]
S_IDLE = 2'd0,
S_SETUP = 2'd1,
S_ACCESS = 2'd2,
S_RESP = 2'd3;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/01_ip_integration/task_11/tb.v:104: $finish called at 85000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_4 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__01_ip_integration__task_11\samples\run_20260426_070416_680227_376b99__sample_4
generated.v previewmodule axi2apb_write_bridge (
input clk,
input rst_n,
input [31:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
output [31:0] paddr,
output psel,
output penable,
output pwrite,
output [31:0] pwdata,
input pready,
input pslverr
);
localparam [1:0]
ST_IDLE = 2'd0,
ST_SETUP = 2'd1,
ST_ACCESS = 2'd2,
ST_RESP = 2'd3;
reg [1:0] st, st_n;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/01_ip_integration/task_11/tb.v:104: $finish called at 85000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_5 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__01_ip_integration__task_11\samples\run_20260426_070416_680227_376b99__sample_5
generated.v previewmodule axi2apb_write_bridge (
input clk,
input rst_n,
// AXI4-Lite Write Channel
input [31:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
// APB4 Master Interface
output [31:0] paddr,
output psel,
output penable,
output pwrite,
output [31:0] pwdata,
input pready,
input pslverr
);
localparam [1:0]
S_IDLE = 2'd0,
S_SETUP = 2'd1,
S_ACCESS = 2'd2,
S_RESP = 2'd3;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/01_ip_integration/task_11/tb.v:104: $finish called at 85000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_6 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__01_ip_integration__task_11\samples\run_20260426_070416_680227_376b99__sample_6
generated.v previewmodule axi2apb_write_bridge (
input clk,
input rst_n,
// AXI4-Lite Write Channel
input [31:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
// APB4 Master Interface
output [31:0] paddr,
output psel,
output penable,
output pwrite,
output [31:0] pwdata,
input pready,
input pslverr
);
localparam [1:0]
S_IDLE = 2'd0,
S_SETUP = 2'd1,
S_ACCESS = 2'd2,
S_RESP = 2'd3;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/01_ip_integration/task_11/tb.v:104: $finish called at 105000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_7 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__01_ip_integration__task_11\samples\run_20260426_070416_680227_376b99__sample_7
generated.v previewmodule axi2apb_write_bridge (
input clk,
input rst_n,
input [31:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
output [31:0] paddr,
output psel,
output penable,
output pwrite,
output [31:0] pwdata,
input pready,
input pslverr
);
localparam [1:0]
S_IDLE = 2'd0,
S_SETUP = 2'd1,
S_ACCESS = 2'd2,
S_RESP = 2'd3;
reg [1:0] state;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/01_ip_integration/task_11/tb.v:104: $finish called at 105000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_8 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__01_ip_integration__task_11\samples\run_20260426_070416_680227_376b99__sample_8
generated.v previewmodule axi2apb_write_bridge (
input clk,
input rst_n,
// AXI4-Lite Write Channel
input [31:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
// APB4 Master Interface
output [31:0] paddr,
output psel,
output penable,
output pwrite,
output [31:0] pwdata,
input pready,
input pslverr
);
localparam [1:0]
S_IDLE = 2'd0,
S_SETUP = 2'd1,
S_ACCESS = 2'd2,
S_RESP = 2'd3;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/01_ip_integration/task_11/tb.v:104: $finish called at 85000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_9 | run_20260426_070416_680227_376b99 | ok | ok | failed | skipped | failed | functional | error |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__01_ip_integration__task_11\samples\run_20260426_070416_680227_376b99__sample_9
generated.v previewmodule axi2apb_write_bridge (
input clk,
input rst_n,
// AXI4-Lite Write Channel
input [31:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
// APB4 Master Interface
output [31:0] paddr,
output psel,
output penable,
output pwrite,
output [31:0] pwdata,
input pready,
input pslverr
);
localparam [1:0]
ST_IDLE = 2'd0,
ST_SETUP = 2'd1,
ST_ACCESS = 2'd2,
ST_RESP = 2'd3;
...
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_error",
"message": "error",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__01_ip_integration__task_11\samples\run_20260426_070416_680227_376b99__sample_10
generated.v previewmodule axi2apb_write_bridge (
input clk,
input rst_n,
// AXI4-Lite Write Channel
input [31:0] awaddr,
input awvalid,
output awready,
input [31:0] wdata,
input wvalid,
output wready,
output [1:0] bresp,
output bvalid,
input bready,
// APB4 Master Interface
output [31:0] paddr,
output psel,
output penable,
output pwrite,
output [31:0] pwdata,
input pready,
input pslverr
);
localparam [1:0]
S_IDLE = 2'd0,
S_SETUP = 2'd1,
S_ACCESS = 2'd2,
S_RESP = 2'd3;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/01_ip_integration/task_11/tb.v:104: $finish called at 85000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|