05_dft_testability / task_52 | jtag_tap_debug
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260426_070416_680227_376b99 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 52 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260426_070416_680227_376b99__sample_1
generated.v previewmodule jtag_tap_debug (
input tck,
input trst_n,
input tms,
input tdi,
output tdo,
input [7:0] dbg_status,
output [7:0] dbg_control
);
localparam [3:0]
IR_IDCODE = 4'b0001,
IR_DBG_CTL = 4'b0010,
IR_DBG_STAT = 4'b0011;
localparam [3:0]
TEST_LOGIC_RESET = 4'd0,
RUN_TEST_IDLE = 4'd1,
SELECT_DR_SCAN = 4'd2,
CAPTURE_DR = 4'd3,
SHIFT_DR = 4'd4,
UPDATE_DR = 4'd5,
SELECT_IR_SCAN = 4'd6,
CAPTURE_IR = 4'd7,
SHIFT_IR = 4'd8,
UPDATE_IR = 4'd9;
reg [3:0] tap_state;
reg [3:0] ir_shift;
reg [3:0] ir_reg;
...
functional details[stdout] ERROR: IDCODE readback failed. Expected A5, got 52 ERROR: DBG_CTL readback failed. Expected 3C, got 1e ERROR: DBG_STAT readback failed. Expected 96, got 4b TEST_FAILED /workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 52",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260426_070416_680227_376b99 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 52 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260426_070416_680227_376b99__sample_2
generated.v previewmodule jtag_tap_debug (
input tck,
input trst_n, // active low async reset
input tms,
input tdi,
output tdo,
input [7:0] dbg_status,
output [7:0] dbg_control
);
// TAP states (minimal subset)
localparam [3:0]
TEST_LOGIC_RESET = 4'd0,
RUN_TEST_IDLE = 4'd1,
SELECT_DR_SCAN = 4'd2,
CAPTURE_DR = 4'd3,
SHIFT_DR = 4'd4,
UPDATE_DR = 4'd5,
SELECT_IR_SCAN = 4'd6,
CAPTURE_IR = 4'd7,
SHIFT_IR = 4'd8,
UPDATE_IR = 4'd9;
reg [3:0] tap_state;
// Instruction register and data register
reg [3:0] ir;
reg [7:0] dr;
// Shift registers for IR/DR (to implement "tdo presents current LSB before shift")
// We update tdo combinationally from current shift register LSB.
wire ir_lsb = ir[0];
...
functional details[stdout] ERROR: IDCODE readback failed. Expected A5, got 52 ERROR: DBG_CTL readback failed. Expected 3C, got 1e ERROR: DBG_STAT readback failed. Expected 96, got 4b TEST_FAILED /workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 52",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260426_070416_680227_376b99__sample_3
generated.v previewmodule jtag_tap_debug (
input tck,
input trst_n,
input tms,
input tdi,
output tdo,
input [7:0] dbg_status,
output [7:0] dbg_control
);
// TAP states (minimal subset)
localparam [3:0]
TEST_LOGIC_RESET = 4'd0,
RUN_TEST_IDLE = 4'd1,
SELECT_DR_SCAN = 4'd2,
CAPTURE_DR = 4'd3,
SHIFT_DR = 4'd4,
UPDATE_DR = 4'd5,
SELECT_IR_SCAN = 4'd6,
CAPTURE_IR = 4'd7,
SHIFT_IR = 4'd8,
UPDATE_IR = 4'd9;
reg [3:0] tap_state;
// Instruction register and data register
reg [3:0] ir_reg;
reg [7:0] dr_reg;
// Shift registers for IR/DR (to implement "tdo presents current LSB before shift")
reg [3:0] ir_shift;
reg [7:0] dr_shift;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_4 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260426_070416_680227_376b99__sample_4
generated.v previewmodule jtag_tap_debug (
input tck,
input trst_n, // active low async reset
input tms,
input tdi,
output tdo,
input [7:0] dbg_status,
output [7:0] dbg_control
);
// TAP states (minimal subset)
localparam [3:0]
TEST_LOGIC_RESET = 4'd0,
RUN_TEST_IDLE = 4'd1,
SELECT_DR_SCAN = 4'd2,
CAPTURE_DR = 4'd3,
SHIFT_DR = 4'd4,
UPDATE_DR = 4'd5,
SELECT_IR_SCAN = 4'd6,
CAPTURE_IR = 4'd7,
SHIFT_IR = 4'd8,
UPDATE_IR = 4'd9;
reg [3:0] tap_state;
// Instruction register and data register
reg [3:0] ir_reg;
reg [7:0] dr_reg;
// Shift registers for IR/DR (to implement LSB-first with tdo-before-shift)
reg [3:0] ir_shift;
reg [7:0] dr_shift;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_5 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260426_070416_680227_376b99__sample_5
generated.v previewmodule jtag_tap_debug (
input tck,
input trst_n, // active low async reset
input tms,
input tdi,
output tdo,
input [7:0] dbg_status,
output [7:0] dbg_control
);
// TAP states (minimal subset)
localparam [3:0]
TEST_LOGIC_RESET = 4'd0,
RUN_TEST_IDLE = 4'd1,
SELECT_DR_SCAN = 4'd2,
CAPTURE_DR = 4'd3,
SHIFT_DR = 4'd4,
UPDATE_DR = 4'd5,
SELECT_IR_SCAN = 4'd6,
CAPTURE_IR = 4'd7,
SHIFT_IR = 4'd8,
UPDATE_IR = 4'd9;
reg [3:0] tap_state;
// Instruction register and data register
reg [3:0] ir;
reg [3:0] ir_shift;
reg [7:0] dr;
reg [7:0] dr_shift;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_6 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260426_070416_680227_376b99__sample_6
generated.v previewmodule jtag_tap_debug (
input tck,
input trst_n, // active low async reset
input tms,
input tdi,
output tdo,
input [7:0] dbg_status,
output [7:0] dbg_control
);
// TAP states (minimal subset)
localparam [3:0]
TEST_LOGIC_RESET = 4'd0,
RUN_TEST_IDLE = 4'd1,
SELECT_DR_SCAN = 4'd2,
CAPTURE_DR = 4'd3,
SHIFT_DR = 4'd4,
UPDATE_DR = 4'd5,
SELECT_IR_SCAN = 4'd6,
CAPTURE_IR = 4'd7,
SHIFT_IR = 4'd8,
UPDATE_IR = 4'd9;
reg [3:0] tap_state;
// Instruction register and data register
reg [3:0] ir;
reg [7:0] dr;
// Shift registers for IR/DR (to implement LSB-first with tdo-before-shift)
reg [3:0] ir_shift;
reg [7:0] dr_shift;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_7 | run_20260426_070416_680227_376b99 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 52 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260426_070416_680227_376b99__sample_7
generated.v previewmodule jtag_tap_debug (
input tck,
input trst_n, // active low async reset
input tms,
input tdi,
output tdo,
input [7:0] dbg_status,
output [7:0] dbg_control
);
// TAP states (minimal subset)
localparam [3:0]
TEST_LOGIC_RESET = 4'd0,
RUN_TEST_IDLE = 4'd1,
SELECT_DR_SCAN = 4'd2,
CAPTURE_DR = 4'd3,
SHIFT_DR = 4'd4,
UPDATE_DR = 4'd5,
SELECT_IR_SCAN = 4'd6,
CAPTURE_IR = 4'd7,
SHIFT_IR = 4'd8,
UPDATE_IR = 4'd9;
reg [3:0] tap_state;
// Instruction register and data register
reg [3:0] ir;
reg [3:0] ir_shift;
reg [7:0] dr;
reg [7:0] dr_shift;
// Output control
...
functional details[stdout] ERROR: IDCODE readback failed. Expected A5, got 52 ERROR: DBG_CTL readback failed. Expected 3C, got 1e ERROR: DBG_STAT readback failed. Expected 96, got 4b TEST_FAILED /workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR: IDCODE readback failed. Expected A5, got 52",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260426_070416_680227_376b99__sample_8
generated.v previewmodule jtag_tap_debug (
input tck,
input trst_n, // active low async reset
input tms,
input tdi,
output tdo,
input [7:0] dbg_status,
output [7:0] dbg_control
);
// TAP states (minimal subset)
localparam [3:0]
TEST_LOGIC_RESET = 4'd0,
RUN_TEST_IDLE = 4'd1,
SELECT_DR_SCAN = 4'd2,
CAPTURE_DR = 4'd3,
SHIFT_DR = 4'd4,
UPDATE_DR = 4'd5,
SELECT_IR_SCAN = 4'd6,
CAPTURE_IR = 4'd7,
SHIFT_IR = 4'd8,
UPDATE_IR = 4'd9;
reg [3:0] tap_state;
// Instruction register and data register
reg [3:0] ir;
reg [3:0] ir_shift;
reg [7:0] dr;
reg [7:0] dr_shift;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_9 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260426_070416_680227_376b99__sample_9
generated.v previewmodule jtag_tap_debug (
input tck,
input trst_n,
input tms,
input tdi,
output tdo,
input [7:0] dbg_status,
output [7:0] dbg_control
);
// TAP states (minimal subset)
localparam [3:0]
TEST_LOGIC_RESET = 4'd0,
RUN_TEST_IDLE = 4'd1,
SELECT_DR_SCAN = 4'd2,
CAPTURE_DR = 4'd3,
SHIFT_DR = 4'd4,
UPDATE_DR = 4'd5,
SELECT_IR_SCAN = 4'd6,
CAPTURE_IR = 4'd7,
SHIFT_IR = 4'd8,
UPDATE_IR = 4'd9;
reg [3:0] tap_state;
// Instruction register and data register
reg [3:0] ir;
reg [3:0] ir_shift;
reg [7:0] dr;
reg [7:0] dr_shift;
// TDO register
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|
| sample_10 | run_20260426_070416_680227_376b99 | ok | ok | ok | ok | ok | success | Full pipeline success |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__05_dft_testability__task_52\samples\run_20260426_070416_680227_376b99__sample_10
generated.v previewmodule jtag_tap_debug (
input tck,
input trst_n, // active low async reset
input tms,
input tdi,
output tdo,
input [7:0] dbg_status,
output [7:0] dbg_control
);
// TAP states (minimal subset)
localparam [3:0]
TEST_LOGIC_RESET = 4'd0,
RUN_TEST_IDLE = 4'd1,
SELECT_DR_SCAN = 4'd2,
CAPTURE_DR = 4'd3,
SHIFT_DR = 4'd4,
UPDATE_DR = 4'd5,
SELECT_IR_SCAN = 4'd6,
CAPTURE_IR = 4'd7,
SHIFT_IR = 4'd8,
UPDATE_IR = 4'd9;
reg [3:0] tap_state;
// Instruction register
reg [3:0] ir_reg;
reg [3:0] ir_shift;
// Data register
reg [7:0] dr_reg;
reg [7:0] dr_shift;
...
functional details[stdout] TEST_PASSED /workspace/banchmarks/pashencev/05_dft_testability/task_52/tb.v:138: $finish called at 692000 (1ps) synthesis details[error] None outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": true,
"openlane_ok": true,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": true,
"success": true
}
|