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gpt-5.4-nano | RAG on

07_csr_register_map_generation / task_72 | axil_sensor_csr

benchmarkilyasov
task_idilyasov/07_csr_register_map_generation/task_72
samples_total10
final_success_samples4
final_success_rate_samples40.0%
functional_pass_rate_samples40.0%
synth_pass_rate_samples40.0%
source_runsrun_20260426_070416_680227_376b99

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_070416_680227_376b99 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write channel was not ready in idle state.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_070416_680227_376b99__sample_1
generated.v preview 
module axil_sensor_csr (
    input              clk,
    input              rst_n,      // active low async reset

    input      [7:0]  awaddr,
    input              awvalid,
    output reg         awready,

    input      [31:0] wdata,
    input      [3:0]  wstrb,
    input              wvalid,
    output reg         wready,

    output reg [1:0]  bresp,
    output reg         bvalid,
    input              bready,

    input      [7:0]  araddr,
    input              arvalid,
    output reg         arready,

    output reg [31:0] rdata,
    output reg [1:0]  rresp,
    output reg         rvalid,
    input              rready,

    input      [7:0]  hw_level,
    input              irq_evt,

    output reg         block_enable,
    output reg [7:0]  gain,
    output reg         kick_pulse,
...
functional details 
[stdout]
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: W1C clear of irq_sticky failed.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write channel was not ready in idle state.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_070416_680227_376b99 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write channel was not ready in idle state.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_070416_680227_376b99__sample_2
generated.v preview 
module axil_sensor_csr (
    input         clk,
    input         rst_n,       // active low async reset

    input  [7:0]  awaddr,
    input         awvalid,
    output        awready,

    input  [31:0] wdata,
    input  [3:0]  wstrb,
    input         wvalid,
    output        wready,

    output [1:0]  bresp,
    output        bvalid,
    input         bready,

    input  [7:0]  araddr,
    input         arvalid,
    output        arready,

    output [31:0] rdata,
    output [1:0]  rresp,
    output        rvalid,
    input         rready,

    input  [7:0]  hw_level,
    input         irq_evt,

    output        block_enable,
    output [7:0]  gain,
    output        kick_pulse,
...
functional details 
[stdout]
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: W1C clear of irq_sticky failed.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write channel was not ready in idle state.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_070416_680227_376b99 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write response was not generated correctly.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_070416_680227_376b99__sample_3
generated.v preview 
module axil_sensor_csr (
  input         clk,
  input         rst_n,      // active low async reset

  input  [7:0]  awaddr,
  input         awvalid,
  output        awready,

  input  [31:0] wdata,
  input  [3:0]  wstrb,
  input         wvalid,
  output        wready,

  output [1:0]  bresp,
  output        bvalid,
  input         bready,

  input  [7:0]  araddr,
  input         arvalid,
  output        arready,

  output [31:0] rdata,
  output [1:0]  rresp,
  output        rvalid,
  input         rready,

  input  [7:0]  hw_level,
  input          irq_evt,

  output         block_enable,
  output [7:0]   gain,
  output         kick_pulse,
...
functional details 
[stdout]
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: STATUS read without IRQ bit set returned wrong value. Got 00000000
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: STATUS read with IRQ bit set returned wrong value. Got 00005c00
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: W1C clear of irq_sticky failed.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: CMD register should read as zero. Got 00005c00
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write response was not generated correctly.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_4 run_20260426_070416_680227_376b99 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write response was not generated correctly.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_070416_680227_376b99__sample_4
generated.v preview 
module axil_sensor_csr (
  input         clk,
  input         rst_n,      // active low async reset

  input  [7:0]  awaddr,
  input         awvalid,
  output        awready,

  input  [31:0] wdata,
  input  [3:0]  wstrb,
  input         wvalid,
  output        wready,

  output [1:0]  bresp,
  output        bvalid,
  input         bready,

  input  [7:0]  araddr,
  input         arvalid,
  output        arready,
  output [31:0] rdata,
  output [1:0]  rresp,
  output        rvalid,
  input         rready,

  input  [7:0]  hw_level,
  input         irq_evt,

  output        block_enable,
  output [7:0]  gain,
  output        kick_pulse,
  output        irq_sticky
...
syntax details 
[stderr]
/data/eval/out/run_20260426_070416_680227_376b99/tmp/gpt5_4_nano/pashencev__07_csr_register_map_generation__task_72/sample_4/generated.v:81: warning: @* found no sensitivities so it will never trigger.
functional details 
[stdout]
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: AXI-Lite read response was not generated correctly.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write response was not generated correctly.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_070416_680227_376b99 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_070416_680227_376b99__sample_5
generated.v preview 
module axil_sensor_csr (
  input         clk,
  input         rst_n,      // active low async reset

  input  [7:0]  awaddr,
  input         awvalid,
  output        awready,

  input  [31:0] wdata,
  input  [3:0]  wstrb,
  input         wvalid,
  output        wready,

  output [1:0]  bresp,
  output        bvalid,
  input         bready,

  input  [7:0]  araddr,
  input         arvalid,
  output        arready,

  output [31:0] rdata,
  output [1:0]  rresp,
  output        rvalid,
  input         rready,

  input  [7:0]  hw_level,
  input         irq_evt,

  output        block_enable,
  output [7:0]  gain,
  output        kick_pulse,
...
functional details 
[stdout]
TEST_PASSED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_6 run_20260426_070416_680227_376b99 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_070416_680227_376b99__sample_6
generated.v preview 
module axil_sensor_csr (
  input         clk,
  input         rst_n,      // active low async reset

  input  [7:0]  awaddr,
  input         awvalid,
  output        awready,

  input  [31:0] wdata,
  input  [3:0]  wstrb,
  input         wvalid,
  output        wready,

  output [1:0]  bresp,
  output        bvalid,
  input         bready,

  input  [7:0]  araddr,
  input         arvalid,
  output        arready,

  output [31:0] rdata,
  output [1:0]  rresp,
  output        rvalid,
  input         rready,

  input  [7:0]  hw_level,
  input         irq_evt,

  output        block_enable,
  output [7:0]  gain,
  output        kick_pulse,
...
syntax details 
[stderr]
/data/eval/out/run_20260426_070416_680227_376b99/tmp/gpt5_4_nano/pashencev__07_csr_register_map_generation__task_72/sample_6/generated.v:75: warning: @* found no sensitivities so it will never trigger.
functional details 
[stdout]
TEST_PASSED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_7 run_20260426_070416_680227_376b99 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write response was not generated correctly.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_070416_680227_376b99__sample_7
generated.v preview 
module axil_sensor_csr (
  input         clk,
  input         rst_n,      // active low async reset

  input  [7:0]  awaddr,
  input         awvalid,
  output        awready,

  input  [31:0] wdata,
  input  [3:0]  wstrb,
  input         wvalid,
  output        wready,

  output [1:0]  bresp,
  output        bvalid,
  input         bready,

  input  [7:0]  araddr,
  input         arvalid,
  output        arready,
  output [31:0] rdata,
  output [1:0]  rresp,
  output        rvalid,
  input         rready,

  input  [7:0]  hw_level,
  input          irq_evt,

  output         block_enable,
  output [7:0]   gain,
  output         kick_pulse,
  output         irq_sticky
...
functional details 
[stdout]
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: W1C clear of irq_sticky failed.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: kick_pulse did not assert on CMD write.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write response was not generated correctly.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_070416_680227_376b99 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write response was not generated correctly.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_070416_680227_376b99__sample_8
generated.v preview 
module axil_sensor_csr (
  input         clk,
  input         rst_n,      // active low async reset

  input  [7:0]  awaddr,
  input         awvalid,
  output        awready,

  input  [31:0] wdata,
  input  [3:0]  wstrb,
  input         wvalid,
  output        wready,

  output [1:0]  bresp,
  output        bvalid,
  input         bready,

  input  [7:0]  araddr,
  input         arvalid,
  output        arready,

  output [31:0] rdata,
  output [1:0]  rresp,
  output        rvalid,
  input         rready,

  input  [7:0]  hw_level,
  input         irq_evt,

  output        block_enable,
  output [7:0]  gain,
  output        kick_pulse,
...
functional details 
[stdout]
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: byte-lane write to CTRL gain field failed.
ERROR: AXI-Lite read response was not generated correctly.
ERROR: AXI-Lite read channel was not ready in idle state.
ERROR: AXI-Lite write response was not generated correctly.
ERROR: AXI-Lite write channel was not ready in idle state.
ERROR: W1C clear of irq_sticky failed.
ERROR: AXI-Lite CMD write response was not generated correctly.
ERROR: kick_pulse did not assert on CMD write.
ERROR: AXI-Lite read response was not generated correctly.
TEST_FAILED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: AXI-Lite write response was not generated correctly.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_070416_680227_376b99 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_070416_680227_376b99__sample_9
generated.v preview 
module axil_sensor_csr (
  input         clk,
  input         rst_n,      // active low async reset

  input  [7:0]  awaddr,
  input         awvalid,
  output        awready,

  input  [31:0] wdata,
  input  [3:0]  wstrb,
  input         wvalid,
  output        wready,

  output [1:0]  bresp,
  output        bvalid,
  input         bready,

  input  [7:0]  araddr,
  input         arvalid,
  output        arready,
  output [31:0] rdata,
  output [1:0]  rresp,
  output        rvalid,
  input         rready,

  input  [7:0]  hw_level,
  input         irq_evt,

  output        block_enable,
  output [7:0]  gain,
  output        kick_pulse,
  output        irq_sticky
...
functional details 
[stdout]
TEST_PASSED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_10 run_20260426_070416_680227_376b99 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\ilyasov\tasks\ilyasov__07_csr_register_map_generation__task_72\samples\run_20260426_070416_680227_376b99__sample_10
generated.v preview 
module axil_sensor_csr (
  input         clk,
  input         rst_n,      // active low async reset

  input  [7:0]  awaddr,
  input         awvalid,
  output        awready,

  input  [31:0] wdata,
  input  [3:0]  wstrb,
  input         wvalid,
  output        wready,

  output [1:0]  bresp,
  output        bvalid,
  input         bready,

  input  [7:0]  araddr,
  input         arvalid,
  output        arready,

  output [31:0] rdata,
  output [1:0]  rresp,
  output        rvalid,
  input         rready,

  input  [7:0]  hw_level,
  input         irq_evt,

  output        block_enable,
  output [7:0]  gain,
  output        kick_pulse,
...
functional details 
[stdout]
TEST_PASSED
/workspace/banchmarks/pashencev/07_csr_register_map_generation/task_72/tb.v:259: $finish called at 206000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}