13_rtllm_arithmetic / task_02 | verified_adder_16bit
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260426_070416_680227_376b99 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_070416_680227_376b99__sample_1
generated.v previewmodule verified_adder_16bit(
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Co
);
wire [15:0] sum;
wire [15:0] c;
adder_8bit u0 (
.a (a[7:0]),
.b (b[7:0]),
.Cin (Cin),
.y (sum[7:0]),
.Co (c[7])
);
adder_8bit u1 (
.a (a[15:8]),
.b (b[15:8]),
.Cin (c[7]),
.y (sum[15:8]),
.Co (Co)
);
assign y = sum;
endmodule
module adder_8bit(
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
adder_16bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_16bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260426_070416_680227_376b99 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_070416_680227_376b99__sample_2
generated.v previewmodule verified_adder_16bit(
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Co
);
wire [8:0] c; // c[0]=Cin, c[8]=carry out of lower 8-bit, c[16] not used
assign c[0] = Cin;
wire [7:0] y0;
wire [7:0] y1;
adder_8bit u_add0(
.a (a[7:0]),
.b (b[7:0]),
.Cin (c[0]),
.y (y0),
.Co (c[8])
);
adder_8bit u_add1(
.a (a[15:8]),
.b (b[15:8]),
.Cin (c[8]),
.y (y1),
.Co (Co)
);
assign y = {y1, y0};
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
adder_16bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_16bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260426_070416_680227_376b99 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_070416_680227_376b99__sample_3
generated.v previewmodule verified_adder_16bit(
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Co
);
wire [8:0] c8; // c8[0]=Cin, c8[8]=carry out of lower 8-bit, c8[8] feeds upper 8-bit
assign c8[0] = Cin;
wire [7:0] y_lo;
wire [7:0] y_hi;
adder_8bit u_lo(
.a (a[7:0]),
.b (b[7:0]),
.Cin (c8[0]),
.y (y_lo),
.Co (c8[8])
);
adder_8bit u_hi(
.a (a[15:8]),
.b (b[15:8]),
.Cin (c8[8]),
.y (y_hi),
.Co (Co)
);
assign y = {y_hi, y_lo};
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
adder_16bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_16bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260426_070416_680227_376b99 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_070416_680227_376b99__sample_4
generated.v previewmodule verified_adder_16bit(
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Co
);
wire [8:0] c; // c[0]=Cin, c[8]=carry into upper 8-bit, c[16] not used
assign c[0] = Cin;
wire [7:0] y0;
wire [7:0] y1;
wire c8;
adder_8bit u_adder0(
.a (a[7:0]),
.b (b[7:0]),
.Cin (c[0]),
.y (y0),
.Co (c8)
);
adder_8bit u_adder1(
.a (a[15:8]),
.b (b[15:8]),
.Cin (c8),
.y (y1),
.Co (Co)
);
assign y = {y1, y0};
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
adder_16bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_16bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260426_070416_680227_376b99 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_070416_680227_376b99__sample_5
generated.v previewmodule verified_adder_16bit(
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Co
);
wire [8:0] c; // c[0]=Cin, c[8]=carry into upper 8-bit, c[16] not used
assign c[0] = Cin;
wire [7:0] y0;
wire co0;
adder_8bit u_adder0(
.a (a[7:0]),
.b (b[7:0]),
.Cin (c[0]),
.y (y0),
.Co (co0)
);
assign c[8] = co0;
assign y[7:0] = y0;
wire [7:0] y1;
wire co1;
adder_8bit u_adder1(
.a (a[15:8]),
.b (b[15:8]),
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
adder_16bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_16bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260426_070416_680227_376b99 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_070416_680227_376b99__sample_6
generated.v previewmodule verified_adder_16bit(
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Co
);
wire [8:0] c; // c[0]=Cin, c[8]=carry out of lower 8-bit, c[8] used as Cin for upper
assign c[0] = Cin;
wire [7:0] y0;
wire co0;
adder_8bit u_adder0(
.a (a[7:0]),
.b (b[7:0]),
.Cin (c[0]),
.y (y0),
.Co (co0)
);
assign c[8] = co0;
wire [7:0] y1;
wire co1;
adder_8bit u_adder1(
.a (a[15:8]),
.b (b[15:8]),
.Cin (c[8]),
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
adder_16bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_16bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260426_070416_680227_376b99 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_070416_680227_376b99__sample_7
generated.v previewmodule verified_adder_16bit(
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Co
);
wire [8:0] c; // c[0]=Cin, c[8]=carry into upper 8-bit, c[16]=Co (via c[8] and final assign)
assign c[0] = Cin;
wire [7:0] y0;
wire Co0;
adder_8bit u_adder0 (
.a (a[7:0]),
.b (b[7:0]),
.Cin (c[0]),
.y (y0),
.Co (Co0)
);
assign y[7:0] = y0;
assign c[8] = Co0;
wire [7:0] y1;
wire Co1;
adder_8bit u_adder1 (
.a (a[15:8]),
.b (b[15:8]),
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
adder_16bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_16bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260426_070416_680227_376b99 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_070416_680227_376b99__sample_8
generated.v previewmodule verified_adder_16bit(
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Co
);
wire [8:0] c; // c[0]=Cin, c[8]=carry into upper 8-bit, c[16]=Co (mapped via c[8] and final)
assign c[0] = Cin;
wire [7:0] y_lo;
wire [7:0] y_hi;
wire co_lo;
wire co_hi;
adder_8bit u_adder_lo(
.a (a[7:0]),
.b (b[7:0]),
.Cin (c[0]),
.y (y_lo),
.Co (co_lo)
);
assign c[8] = co_lo;
adder_8bit u_adder_hi(
.a (a[15:8]),
.b (b[15:8]),
.Cin (c[8]),
.y (y_hi),
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
adder_16bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_16bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260426_070416_680227_376b99 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_070416_680227_376b99__sample_9
generated.v previewmodule verified_adder_16bit(
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Co
);
wire [8:0] c; // c[0]=Cin, c[8]=carry into upper 8-bit, c[16] unused
assign c[0] = Cin;
wire [7:0] y0;
wire co0;
wire [7:0] y1;
wire co1;
adder_8bit u_adder0(
.a (a[7:0]),
.b (b[7:0]),
.Cin(c[0]),
.y (y0),
.Co(co0)
);
assign c[8] = co0;
adder_8bit u_adder1(
.a (a[15:8]),
.b (b[15:8]),
.Cin(c[8]),
.y (y1),
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
adder_16bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_16bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260426_070416_680227_376b99 | ok | ok | failed | skipped | failed | functional | /workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\gpt-5-4-nano\rag_on\benchmarks\rtllm\tasks\rtllm__13_rtllm_arithmetic__task_02\samples\run_20260426_070416_680227_376b99__sample_10
generated.v previewmodule verified_adder_16bit(
input [15:0] a,
input [15:0] b,
input Cin,
output [15:0] y,
output Co
);
wire [8:0] c; // c[0]=Cin, c[8]=carry into upper 8-bit, c[16] not used
assign c[0] = Cin;
wire [7:0] y0;
wire co0;
adder_8bit u_adder0(
.a (a[7:0]),
.b (b[7:0]),
.Cin (c[0]),
.y (y0),
.Co (co0)
);
assign c[8] = co0;
wire [7:0] y1;
wire co1;
adder_8bit u_adder1(
.a (a[15:8]),
.b (b[15:8]),
.Cin (c[8]),
...
functional details[stderr]
/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit
3 error(s) during elaboration.
*** These modules were missing:
adder_16bit referenced 1 times.
***
synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.testbench_failed",
"message": "/workspace/banchmarks/rtllm/13_rtllm_arithmetic/task_02/tb.v:39: error: Unknown module type: adder_16bit\n3 error(s) during elaboration.\n*** These modules were missing:\n adder_16bit referenced 1 times.\n***\n",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|