10_fault_tolerant_safety / task_101 | lockstep_event_counter
Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.
| sample | run | extract_ok | syntax_ok | functional_ok | openlane_ok | final_success | failure_stage | failure_reason | details |
|---|---|---|---|---|---|---|---|---|---|
| sample_1 | run_20260425_215014_451219_c08f66 | failed | failed | failed | skipped | failed | extract | Model response is empty |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen2-5-coder-14b\rag_on\benchmarks\ilyasov\tasks\ilyasov__10_fault_tolerant_safety__task_101\samples\run_20260425_215014_451219_c08f66__sample_1
synthesis details[error] None errors[][
{
"stage": "model_request",
"code": "model_request.failed",
"message": "500 Server Error: Internal Server Error for url: http://ollama:11434/api/chat",
"retryable": true,
"details": {}
},
{
"stage": "extract",
"code": "extract.no_verilog_found",
"message": "Model response is empty",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": false,
"extract_ok": false,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_2 | run_20260425_215014_451219_c08f66 | failed | failed | failed | skipped | failed | extract | Model response is empty |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen2-5-coder-14b\rag_on\benchmarks\ilyasov\tasks\ilyasov__10_fault_tolerant_safety__task_101\samples\run_20260425_215014_451219_c08f66__sample_2
synthesis details[error] None errors[][
{
"stage": "model_request",
"code": "model_request.failed",
"message": "500 Server Error: Internal Server Error for url: http://ollama:11434/api/chat",
"retryable": true,
"details": {}
},
{
"stage": "extract",
"code": "extract.no_verilog_found",
"message": "Model response is empty",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": false,
"extract_ok": false,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_3 | run_20260425_215014_451219_c08f66 | failed | failed | failed | skipped | failed | extract | Model response is empty |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen2-5-coder-14b\rag_on\benchmarks\ilyasov\tasks\ilyasov__10_fault_tolerant_safety__task_101\samples\run_20260425_215014_451219_c08f66__sample_3
synthesis details[error] None errors[][
{
"stage": "model_request",
"code": "model_request.failed",
"message": "500 Server Error: Internal Server Error for url: http://ollama:11434/api/chat",
"retryable": true,
"details": {}
},
{
"stage": "extract",
"code": "extract.no_verilog_found",
"message": "Model response is empty",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": false,
"extract_ok": false,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_4 | run_20260425_215014_451219_c08f66 | failed | failed | failed | skipped | failed | extract | Model response is empty |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen2-5-coder-14b\rag_on\benchmarks\ilyasov\tasks\ilyasov__10_fault_tolerant_safety__task_101\samples\run_20260425_215014_451219_c08f66__sample_4
synthesis details[error] None errors[][
{
"stage": "model_request",
"code": "model_request.failed",
"message": "500 Server Error: Internal Server Error for url: http://ollama:11434/api/chat",
"retryable": true,
"details": {}
},
{
"stage": "extract",
"code": "extract.no_verilog_found",
"message": "Model response is empty",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": false,
"extract_ok": false,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_5 | run_20260425_215014_451219_c08f66 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR (step 1): count=0 expected=1 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen2-5-coder-14b\rag_on\benchmarks\ilyasov\tasks\ilyasov__10_fault_tolerant_safety__task_101\samples\run_20260425_215014_451219_c08f66__sample_5
generated.v previewmodule lockstep_event_counter (
input wire clk,
input wire rst_n,
input wire load,
input wire step,
input wire [3:0] load_value,
input wire inject_shadow_fault,
output reg [3:0] count,
output reg count_valid,
output reg fault_flag,
output reg halted
);
reg [3:0] primary;
reg [3:0] shadow;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
primary <= 4'h0;
shadow <= 4'h0;
count <= 4'h0;
count_valid <= 1'b0;
fault_flag <= 1'b0;
halted <= 1'b0;
end else if (fault_flag) begin
primary <= 4'h0;
shadow <= 4'h0;
count <= 4'h0;
count_valid <= 1'b0;
halted <= 1'b1;
end else begin
if (load) begin
...
functional details[stdout] ERROR (step 1): count=0 expected=1 ERROR (step 2): count=1 expected=2 ERROR (load priority): count=2 expected=c ERROR (fault detection and safe state): count=2 expected=0 ERROR (fault detection and safe state): count_valid=1 expected=0 ERROR (fault detection and safe state): halted=0 expected=1 ERROR (reload after reset): count=0 expected=5 ERROR (step after reset): count=5 expected=6 TEST_FAILED /workspace/banchmarks/pashencev/10_fault_tolerant_safety/task_101/tb.v:148: $finish called at 106000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR (step 1): count=0 expected=1",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_6 | run_20260425_215014_451219_c08f66 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR (step 1): count=0 expected=1 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen2-5-coder-14b\rag_on\benchmarks\ilyasov\tasks\ilyasov__10_fault_tolerant_safety__task_101\samples\run_20260425_215014_451219_c08f66__sample_6
generated.v previewmodule lockstep_event_counter (
input wire clk,
input wire rst_n,
input wire load,
input wire step,
input wire [3:0] load_value,
input wire inject_shadow_fault,
output reg [3:0] count,
output reg count_valid,
output reg fault_flag,
output reg halted
);
reg [3:0] primary;
reg [3:0] shadow;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
primary <= 4'h0;
shadow <= 4'h0;
count <= 4'h0;
count_valid <= 1'b0;
fault_flag <= 1'b0;
halted <= 1'b0;
end else if (fault_flag) begin
primary <= 4'h0;
shadow <= 4'h0;
count <= 4'h0;
count_valid <= 1'b0;
halted <= 1'b1;
end else begin
if (load) begin
...
functional details[stdout] ERROR (step 1): count=0 expected=1 ERROR (step 2): count=1 expected=2 ERROR (load priority): count=2 expected=c ERROR (fault detection and safe state): count=2 expected=0 ERROR (fault detection and safe state): count_valid=1 expected=0 ERROR (fault detection and safe state): halted=0 expected=1 ERROR (reload after reset): count=0 expected=5 ERROR (step after reset): count=5 expected=6 TEST_FAILED /workspace/banchmarks/pashencev/10_fault_tolerant_safety/task_101/tb.v:148: $finish called at 106000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR (step 1): count=0 expected=1",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_7 | run_20260425_215014_451219_c08f66 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR (step 1): count=0 expected=1 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen2-5-coder-14b\rag_on\benchmarks\ilyasov\tasks\ilyasov__10_fault_tolerant_safety__task_101\samples\run_20260425_215014_451219_c08f66__sample_7
generated.v previewmodule lockstep_event_counter (
input wire clk,
input wire rst_n,
input wire load,
input wire step,
input wire [3:0] load_value,
input wire inject_shadow_fault,
output reg [3:0] count,
output reg count_valid,
output reg fault_flag,
output reg halted
);
reg [3:0] primary;
reg [3:0] shadow;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
primary <= 4'h0;
shadow <= 4'h0;
count <= 4'h0;
count_valid <= 1'b0;
fault_flag <= 1'b0;
halted <= 1'b0;
end else if (fault_flag) begin
primary <= 4'h0;
shadow <= 4'h0;
count <= 4'h0;
count_valid <= 1'b0;
halted <= 1'b1;
end else begin
if (load) begin
...
functional details[stdout] ERROR (step 1): count=0 expected=1 ERROR (step 2): count=1 expected=2 ERROR (load priority): count=2 expected=c ERROR (fault detection and safe state): count=2 expected=0 ERROR (fault detection and safe state): count_valid=1 expected=0 ERROR (fault detection and safe state): halted=0 expected=1 ERROR (reload after reset): count=0 expected=5 ERROR (step after reset): count=5 expected=6 TEST_FAILED /workspace/banchmarks/pashencev/10_fault_tolerant_safety/task_101/tb.v:148: $finish called at 106000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR (step 1): count=0 expected=1",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_8 | run_20260425_215014_451219_c08f66 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR (step 1): count=0 expected=1 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen2-5-coder-14b\rag_on\benchmarks\ilyasov\tasks\ilyasov__10_fault_tolerant_safety__task_101\samples\run_20260425_215014_451219_c08f66__sample_8
generated.v previewmodule lockstep_event_counter (
input wire clk,
input wire rst_n,
input wire load,
input wire step,
input wire [3:0] load_value,
input wire inject_shadow_fault,
output reg [3:0] count,
output reg count_valid,
output reg fault_flag,
output reg halted
);
reg [3:0] primary;
reg [3:0] shadow;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
primary <= 4'h0;
shadow <= 4'h0;
count <= 4'h0;
count_valid <= 1'b0;
fault_flag <= 1'b0;
halted <= 1'b0;
end else if (fault_flag) begin
primary <= 4'h0;
shadow <= 4'h0;
count <= 4'h0;
count_valid <= 1'b0;
halted <= 1'b1;
end else begin
if (load) begin
...
functional details[stdout] ERROR (step 1): count=0 expected=1 ERROR (step 2): count=1 expected=2 ERROR (load priority): count=2 expected=c ERROR (fault detection and safe state): count=2 expected=0 ERROR (fault detection and safe state): count_valid=1 expected=0 ERROR (fault detection and safe state): halted=0 expected=1 ERROR (reload after reset): count=0 expected=5 ERROR (step after reset): count=5 expected=6 TEST_FAILED /workspace/banchmarks/pashencev/10_fault_tolerant_safety/task_101/tb.v:148: $finish called at 106000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR (step 1): count=0 expected=1",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_9 | run_20260425_215014_451219_c08f66 | ok | ok | failed | failed | failed | functional | Functional output contains failure marker: TEST_FAILED. ERROR (step 1): count=0 expected=1 |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen2-5-coder-14b\rag_on\benchmarks\ilyasov\tasks\ilyasov__10_fault_tolerant_safety__task_101\samples\run_20260425_215014_451219_c08f66__sample_9
generated.v previewmodule lockstep_event_counter (
input clk,
input rst_n,
input load,
input step,
input [3:0] load_value,
input inject_shadow_fault,
output reg [3:0] count,
output reg count_valid,
output reg fault_flag,
output reg halted
);
reg [3:0] primary;
reg [3:0] shadow;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
primary <= 4'h0;
shadow <= 4'h0;
count <= 4'h0;
count_valid <= 1'b0;
fault_flag <= 1'b0;
halted <= 1'b0;
end else if (fault_flag) begin
primary <= 4'h0;
shadow <= 4'h0;
count <= 4'h0;
count_valid <= 1'b0;
halted <= 1'b1;
end else begin
if (load) begin
...
functional details[stdout] ERROR (step 1): count=0 expected=1 ERROR (step 2): count=1 expected=2 ERROR (load priority): count=2 expected=c ERROR (fault detection and safe state): count=2 expected=0 ERROR (fault detection and safe state): count_valid=1 expected=0 ERROR (fault detection and safe state): halted=0 expected=1 ERROR (reload after reset): count=0 expected=5 ERROR (step after reset): count=5 expected=6 TEST_FAILED /workspace/banchmarks/pashencev/10_fault_tolerant_safety/task_101/tb.v:148: $finish called at 106000 (1ps) synthesis details[error] None errors[][
{
"stage": "functional",
"code": "functional.output_failed_marker",
"message": "Functional output contains failure marker: TEST_FAILED. ERROR (step 1): count=0 expected=1",
"retryable": false,
"details": {
"marker": "TEST_FAILED"
}
},
{
"stage": "openlane",
"code": "openlane.invalidated_by_functional_failure",
"message": "OpenLane result invalidated because functional validation failed after output-marker correction",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": true,
"extract_ok": true,
"syntax_ok": true,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|
| sample_10 | run_20260425_215014_451219_c08f66 | failed | failed | failed | skipped | failed | extract | Model response is empty |
Open detailssample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen2-5-coder-14b\rag_on\benchmarks\ilyasov\tasks\ilyasov__10_fault_tolerant_safety__task_101\samples\run_20260425_215014_451219_c08f66__sample_10
synthesis details[error] None errors[][
{
"stage": "model_request",
"code": "model_request.failed",
"message": "500 Server Error: Internal Server Error for url: http://ollama:11434/api/chat",
"retryable": true,
"details": {}
},
{
"stage": "extract",
"code": "extract.no_verilog_found",
"message": "Model response is empty",
"retryable": false,
"details": {}
}
]
outcome{
"llm_ok": false,
"extract_ok": false,
"syntax_ok": false,
"functional_ok": false,
"openlane_ok": false,
"syntax_required": true,
"functional_required": true,
"openlane_required": true,
"final_success": false,
"success": false
}
|