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qwen3-coder:30b | RAG off

06_reset_domain_crossing / task_60 | reset_sync_2ff

benchmarkilyasov
task_idilyasov/06_reset_domain_crossing/task_60
samples_total10
final_success_samples4
final_success_rate_samples40.0%
functional_pass_rate_samples40.0%
synth_pass_rate_samples40.0%
source_runsrun_20260426_175047_007550_9b8266

Что показывает эта страница

Здесь перечислены все реальные попытки этой модели на одной задаче. По каждой попытке можно увидеть, до какой стадии она дошла, где именно сломалась и какое сообщение об ошибке вернулось из syntax, functional или synthesis.

Samples

sample run extract_ok syntax_ok functional_ok openlane_ok final_success failure_stage failure_reason details
sample_1 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260426_175047_007550_9b8266__sample_1
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output srst_n
);

reg [1:0] sync_reset;
reg srst_n_reg;

always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        sync_reset <= 2'b00;
        srst_n_reg <= 1'b0;
    end else begin
        if (sync_reset == 2'b00) begin
            sync_reset <= 2'b01;
        end else if (sync_reset == 2'b01) begin
            sync_reset <= 2'b11;
        end else begin
            sync_reset <= 2'b11;
        end
        srst_n_reg <= (sync_reset == 2'b11) ? 1'b1 : 1'b0;
    end
end

assign srst_n = srst_n_reg;

endmodule
functional details 
[stdout]
ERROR: local reset did not deassert after two clock edges.
ERROR: restart sequence failed to release reset after two edges.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_2 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260426_175047_007550_9b8266__sample_2
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output srst_n
);

reg [1:0] sync_reset;
reg srst_n_reg;

always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        sync_reset <= 2'b00;
        srst_n_reg <= 1'b0;
    end else begin
        if (sync_reset == 2'b00) begin
            sync_reset <= 2'b01;
        end else if (sync_reset == 2'b01) begin
            sync_reset <= 2'b11;
        end else begin
            sync_reset <= 2'b11;
        end
        srst_n_reg <= (sync_reset == 2'b11) ? 1'b1 : 1'b0;
    end
end

assign srst_n = srst_n_reg;

endmodule
functional details 
[stdout]
ERROR: local reset did not deassert after two clock edges.
ERROR: restart sequence failed to release reset after two edges.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_3 run_20260426_175047_007550_9b8266 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260426_175047_007550_9b8266__sample_3
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output srst_n
);

reg [1:0] sync_reset;
reg srst_n_reg;

always @(posedge clk or negedge arst_n) begin
    if (!arst_n)
        sync_reset <= 2'b00;
    else begin
        if (sync_reset == 2'b00)
            sync_reset <= 2'b01;
        else if (sync_reset == 2'b01)
            sync_reset <= 2'b11;
        else
            sync_reset <= 2'b11;
    end
end

assign srst_n = sync_reset[1];

endmodule
functional details 
[stdout]
TEST_PASSED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_4 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260426_175047_007550_9b8266__sample_4
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output srst_n
);

reg [1:0] sync_reset;
reg srst_n_reg;

always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        sync_reset <= 2'b00;
        srst_n_reg <= 1'b0;
    end else begin
        if (sync_reset == 2'b00) begin
            sync_reset <= 2'b01;
        end else if (sync_reset == 2'b01) begin
            sync_reset <= 2'b11;
        end else begin
            sync_reset <= 2'b11;
        end
        srst_n_reg <= (sync_reset == 2'b11) ? 1'b1 : 1'b0;
    end
end

assign srst_n = srst_n_reg;

endmodule
functional details 
[stdout]
ERROR: local reset did not deassert after two clock edges.
ERROR: restart sequence failed to release reset after two edges.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_5 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260426_175047_007550_9b8266__sample_5
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output srst_n
);

reg [1:0] sync_reset;
reg srst_n_reg;

always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        sync_reset <= 2'b00;
        srst_n_reg <= 1'b0;
    end else begin
        if (sync_reset == 2'b00) begin
            sync_reset <= 2'b01;
        end else if (sync_reset == 2'b01) begin
            sync_reset <= 2'b11;
        end else begin
            sync_reset <= 2'b11;
        end
        srst_n_reg <= (sync_reset == 2'b11) ? 1'b1 : 1'b0;
    end
end

assign srst_n = srst_n_reg;

endmodule
functional details 
[stdout]
ERROR: local reset did not deassert after two clock edges.
ERROR: restart sequence failed to release reset after two edges.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_6 run_20260426_175047_007550_9b8266 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260426_175047_007550_9b8266__sample_6
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output srst_n
);

reg [1:0] sync_reset;
reg srst_n_reg;

always @(posedge clk or negedge arst_n) begin
    if (!arst_n)
        sync_reset <= 2'b00;
    else begin
        if (sync_reset == 2'b00)
            sync_reset <= 2'b01;
        else if (sync_reset == 2'b01)
            sync_reset <= 2'b11;
        else
            sync_reset <= 2'b11;
    end
end

assign srst_n = sync_reset[1];

endmodule
functional details 
[stdout]
TEST_PASSED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_7 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260426_175047_007550_9b8266__sample_7
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output srst_n
);

reg [1:0] sync_reset;
reg srst_n_reg;

always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        sync_reset <= 2'b00;
        srst_n_reg <= 1'b0;
    end else begin
        if (sync_reset == 2'b00) begin
            sync_reset <= 2'b01;
        end else if (sync_reset == 2'b01) begin
            sync_reset <= 2'b11;
        end else begin
            sync_reset <= 2'b11;
        end
        srst_n_reg <= (sync_reset == 2'b11) ? 1'b1 : 1'b0;
    end
end

assign srst_n = srst_n_reg;

endmodule
functional details 
[stdout]
ERROR: local reset did not deassert after two clock edges.
ERROR: restart sequence failed to release reset after two edges.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_8 run_20260426_175047_007550_9b8266 ok ok failed failed failed functional Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260426_175047_007550_9b8266__sample_8
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output srst_n
);

reg [1:0] sync_reset;
reg srst_n_reg;

always @(posedge clk or negedge arst_n) begin
    if (!arst_n) begin
        sync_reset <= 2'b00;
        srst_n_reg <= 1'b0;
    end else begin
        if (sync_reset == 2'b00) begin
            sync_reset <= 2'b01;
        end else if (sync_reset == 2'b01) begin
            sync_reset <= 2'b11;
        end else begin
            sync_reset <= 2'b11;
        end
        srst_n_reg <= (sync_reset == 2'b11) ? 1'b1 : 1'b0;
    end
end

assign srst_n = srst_n_reg;

endmodule
functional details 
[stdout]
ERROR: local reset did not deassert after two clock edges.
ERROR: restart sequence failed to release reset after two edges.
TEST_FAILED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
errors[] 
[
  {
    "stage": "functional",
    "code": "functional.output_failed_marker",
    "message": "Functional output contains failure marker: TEST_FAILED. ERROR: local reset did not deassert after two clock edges.",
    "retryable": false,
    "details": {
      "marker": "TEST_FAILED"
    }
  },
  {
    "stage": "openlane",
    "code": "openlane.invalidated_by_functional_failure",
    "message": "OpenLane result invalidated because functional validation failed after output-marker correction",
    "retryable": false,
    "details": {}
  }
]
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": false,
  "openlane_ok": false,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": false,
  "success": false
}
sample_9 run_20260426_175047_007550_9b8266 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260426_175047_007550_9b8266__sample_9
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output srst_n
);

reg [1:0] sync_reset;
reg srst_n_reg;

always @(posedge clk or negedge arst_n) begin
    if (!arst_n)
        sync_reset <= 2'b00;
    else begin
        if (sync_reset == 2'b00)
            sync_reset <= 2'b01;
        else if (sync_reset == 2'b01)
            sync_reset <= 2'b11;
        else
            sync_reset <= 2'b11;
    end
end

assign srst_n = sync_reset[1];

endmodule
functional details 
[stdout]
TEST_PASSED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}
sample_10 run_20260426_175047_007550_9b8266 ok ok ok ok ok success Full pipeline success
Open details
sample_dir: E:\Work\MIEM\VKR\Analyse\data\model_dataset\models\qwen3-coder-30b\rag_off\benchmarks\ilyasov\tasks\ilyasov__06_reset_domain_crossing__task_60\samples\run_20260426_175047_007550_9b8266__sample_10
generated.v preview 
module reset_sync_2ff (
    input clk,
    input arst_n,
    output srst_n
);

reg [1:0] sync_reset;
reg srst_n_reg;

always @(posedge clk or negedge arst_n) begin
    if (!arst_n)
        sync_reset <= 2'b00;
    else begin
        if (sync_reset == 2'b00)
            sync_reset <= 2'b01;
        else if (sync_reset == 2'b01)
            sync_reset <= 2'b11;
        else
            sync_reset <= 2'b11;
    end
end

assign srst_n = sync_reset[1];

endmodule
functional details 
[stdout]
TEST_PASSED
/workspace/banchmarks/pashencev/06_reset_domain_crossing/task_60/tb.v:87: $finish called at 56000 (1ps)
synthesis details 
[error]
None
outcome 
{
  "llm_ok": true,
  "extract_ok": true,
  "syntax_ok": true,
  "functional_ok": true,
  "openlane_ok": true,
  "syntax_required": true,
  "functional_required": true,
  "openlane_required": true,
  "final_success": true,
  "success": true
}